Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2 Registers (Continued)
Bit Position |
Bit Name |
Description |
14 |
SPME |
Power Management Event (Set). A write of 1 to this bit sets the PME bit for this function. A write of 0 has no effect. Always reads 0. |
15 |
PME |
Power Management Event (Status/Clear). 1= A power management event has been detected for this function. This is an alias of the PME bit in the Power Management Control/Status Register in PCI Configuration Space for this function. A write of 1 to this bit clears PME. 0= A write of 0 has no effect. |
DSP Powe rd own (PWRPx ) Re g iste rs
These two registers share the following bit layout. One register corresponds to each DSP.
! All bits in this register reset to zero.
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions
Bit Position |
Bit Name |
Description |
0 |
PD |
DSP PowerDown. When written to a 1, causes the DSP to power down (enter its power-down handler). Can also be used to abort a power-up: if the DSP is in the power-down handler after executing an IDLE, writing a 1 will cause the DSP to immediately re-enter the PowerDown interrupt handler after it executes the RTI. When read, PD=1 indicates that this DSP is powered down: either (a) it is in the powerdown handler and has executed an IDLE instruction), and/or (b) the DSP Clock Generator (PLL) is not running and stable. When both DSPs are powered down, the DSP Clock Generator is powered down, and automatically restarts when either DSP wakes up. Note: DSP memory cannot be accessed via PCI or USB when the DSP is powered down. There is a delay after powering up the DSPs with the PU bit during which memory reads must not be performed, because the XTAL or the DSP PLL is not yet running and stable. After powering up by writing a 1 to the PU bit, the PD bit must be polled until it becomes 0, after which the clock generator will be running and it is safe to access DSP memory again. |
1 |
PU |
DSP PowerUp. When written to a 1, causes the DSP to power up (exit the IDLE within its power-down handler). Can also be used to abort a powerdown: when written to 1 while the DSP is within its powerdown handler prior to the IDLE, writing a 1 will cause execution to immediately continue through the IDLE without stopping clocks. When read, PU=1 indicates that this DSP is in the powerdown interrupt handler, whether or not it has executed the powerdown IDLE. |
Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions (Continued)
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