The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 11

Table B-9. SPROMCTL Register Bit Descriptions

Host Mailbox Registers

The Host Mailbox registers control communication between the DSP and host (PCI host or USB Host), depending on which one is turned on. Only one can be active at time.

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DSP Mailbox registers allow you to construct an efficient communications protocol between the PCI device driver and the DSP code. The mailbox functions consist of an InBox0, InBox1, OutBox0, OutBox1, a control register, and a status register.

InBoxes. The incoming mailboxes (InBox0 and InBox1) are 16 bits wide. They may be read or written by the PCI device or the DSP core. PCI writes to the InBoxes may generate DSP interrupts. DSP reads of InBoxes may generate PCI interrupts.

OutBoxes. The outgoing mailboxes (OutBox0 and OutBox1) are 16 bits wide. They may be read or written by the PCI device or the DSP core. DSP writes to the OutBoxes may generate PCI interrupts.

PCI reads of OutBoxes may generate DSP interrupts with special handling. The PC host must perform the following sequence when reading an OutBox: (1) read OutBox, (2) write a 1 to the OutBox Valid bit to clear it. (PCI reads of OutBoxes cannot generate interrupts directly, as they would be “read side-effects” which are prohibited by system design considerations in the PCI Specification.)

Control. This register consists of read/write interrupt enable control bits. (denoted R/W).

Status. This register consists of read/write-one-clear status bits (denoted R/WC). A read/write-one-clear bit is cleared when a one is written to it.

Writing a zero has no effect.

Table B-10 lists the Peripheral Device Control Register Space for PCI/USB Mailbox registers. For register bit names and descriptions for each register, see the topic “Using DSP and PCI Mailbox Registers” in Chapter 6 Dual DSP Cores.

Table B-10. PCI / USB Mailbox Registers

C a rdBus Func tion Ev e nt Re g iste rs