#define PCI_Tx0BADDRL 0x10 // Tx0 DMA Base Address Bits 15:0 #define PCI_Tx0BADDRH 0x12 // Tx0 DMA Base Address Bits 31:16
#define PCI_Tx0CURADDRL 0x14 // Tx0 DMA Current Address Bits 15:0
#define PCI_Tx0CURADDRH 0x16 // Tx0 DMA Current Address Bits 31:16
#define PCI_Tx0BCNTL 0x18 // Tx0 DMA Base Count Bits 15:0
#define PCI_Tx0BCNTH 0x1A // Tx0 DMA Base Count Bits 31:16 #define PCI_Tx0CURCNTL 0x1C // Tx0 DMA Current Count Bits 15:0
#define PCI_Tx0CURCNTH 0x1E // Tx0 DMA Current Count Bits 31:16
#define PCI_Rx1BADDRL 0x20 // Rx1 DMA Base Address Bits 15:0 #define PCI_Rx1BADDRH 0x22 // Rx1 DMA Base Address Bits 31:16
#define PCI_Rx1CURADDRL 0x24 // Rx1 DMA Current Address Bits 15:0
#define PCI_Rx1CURADDRH 0x26 // Rx1 DMA Current Address Bits 31:16
#define PCI_Rx1BCNTL 0x28 // Rx1 DMA Base Count Bits 15:0
#define PCI_Rx1BCNTH 0x2A // Rx1 DMA Base Count Bits 31:16 #define PCI_Rx1CURCNTL 0x2C // Rx1 DMA Current Count Bits 15:0
#define PCI_Rx1CURCNTH 0x2E // Rx1 DMA Current Count Bits 31:16
#define PCI_Tx1BADDRL 0x30 // Tx1 DMA Base Address Bits 15:0 #define PCI_Tx1BADDRH 0x32 // Tx1 DMA Base Address Bits 31:16
#define PCI_Tx1CURADDRL 0x34 // Tx1 DMA Current Address Bits 15:0
#define PCI_Tx1CURADDRh 0x36 // Tx1 DMA Current Address Bits 31:16
#define PCI_Tx1BCNTL 0x38 // Tx1 DMA Base Count Bits 15:0
#define PCI_Tx1BCNTH 0x3A // Tx1 DMA Base Count Bits 31:16 #define PCI_Tx1CURCNTL 0x3C // Tx1 DMA Current Count Bits 15:0
#define PCI_Tx1CURCNTH 0x3E // Tx1 DMA Current Count Bits 31:16
#define PCI_Rx0IRQCNTL 0x40 // Rx0 DMA Interrupt Count Bits 15:0
#define PCI_Rx0IRQCNTH 0x42 // Rx0 DMA Interrupt Count Bits 23:16
#define PCI_Rx0IRQBCNTL 0x44//Rx0 DMA Interrupt Base Count Bits 15:0
#define PCI_Rx0IRQBCNTH 0x46//Rx0 DMA Interrupt Base Count Bits 23:16
#define PCI_Tx0IRQCNTL 0x48 // Tx0 DMA Interrupt Count Bits 15:0
#define PCI_Tx0IRQCNTH 0x4A // Tx0 DMA Interrupt Count Bits 23:16
#define PCI_Tx0IRQBCNTL 0x4C//Tx0 DMA Interrupt Base Count Bits 15:0
#define PCI_Tx0IRQBCNTH 0x4E//Tx0 DMA Interrupt Base Count Bits 23:16
#define PCI_Rx1IRQCNTL 0x50 // Rx1 DMA Interrupt Count Bits 15:0
#define PCI_Rx1IRQCNTH 0x52 // Rx1 DMA Interrupt Count Bits 23:16
#define PCI_Rx1IRQBCNTL 0x54//Rx1 DMA Interrupt Base Count Bits 15:0
#define PCI_Rx1IRQBCNTH 0x56//Rx1 DMA Interrupt Base Count Bits 23:16 #define PCI_Tx1IRQCNTL 0x58 // Tx1 DMA Interrupt Count Bits 15:0 #define PCI_Tx1IRQCNTH 0x5A // Tx1 DMA Interrupt Count Bits 23:16
#define PCI_Tx1IRQBCNTL 0x5C//Tx1 DMA Interrupt Base Count Bits 15:0
#define PCI_Tx1IRQBCNTH 0x5E//Tx1 DMA Interrupt Base Count Bits 23:16
#define PCI_Rx0CTL 0x60 // Rx0 DMA PCI Control/Status
#define PCI_Tx0CTL 0x68 // Tx0 DMA PCI Control/Status
#define PCI_Rx1CTL 0x70 // Rx1 DMA PCI Control/Status
#define PCI_Tx1CTL 0x78 // Tx1 DMA PCI Control/Status
#define PCI_MSTRCNT0 0x80 // DMA Transfer Count0 Bus master // sample transfer count 0.
#define PCI_MSTRCNT1 0x82 // DMA Transfer Count1 Bus master // sample transfer count 1.
#define PCI_DMAC0 0x84 // DMA Control0 Bus master control // and status 0.
#define PCI_DMAC1 0x86 // DMA Control1 Bus master control // and status 1.
#define PCI_IRQSTAT 0x88 // PCI Interrupt Register Status bits for all PCI interrupt sources.
#define PCI_CFGCTL 0x8A // PCI Control Includes config // register read/write control.
// PCI FUNCTION 0 Configuration Space Registers (DSP IOPAGE=0x09)
// Note: Access to these registers is controlled by the PCI RDY bit in the // Chip Mode/Status Register (Page 0x00, Address 0x00).
#define PCI_VendorID0 0x00 // Configuration 0 Vendor ID
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