The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 39

#define RX1ADDR     0x54    // DMA Address,       Fifo1 Receive

#define RX1NXTADDR  0x55    // DMA Next Address,  Fifo1 Receive #define RX1CNT      0x56    // DMA Count,         Fifo1 Receive #define RX1CURCNT   0x57    // DMA Current Count, Fifo1 Receive

// GPIO Control Registers (DSP IOPAGE=0x00)

#define GPIOCFG 0x10 // PIO Config Direction Control (1 = in, 0 = out)

#define GPIOPOL 0x12 // GPIO Polarity

//(Inputs: 0 = active hi, 1 = active lo;

//Outputs: 0 = CMOS, 1 = Open Drain)

#define GPIOSTKY 0x14 // GPIO Sticky: 1 = sticky, 0 = not sticky

#define GPIOWAKECTL 0x16 // GPIO Wake Control

// 1 = wake-up enabled (requires sticky set)

#define GPIOSTAT 0x18 //GPIO Status (Read = Pin state;    // Write: 0 = clear sticky status, 1 = no effect)

#define GPIOCTL 0x1A // GPIO Control(w), Init(r)

//(Read = Power-on state; Write : Set state of output pins) #define GPIOPUP  0x1C // GPIO Pull-up Pull-up enable (if input):    // 1 = enable, 0 = hi-Z

#define GPIOPDN 0x1E // GPIO Pull-down Pull-down enable (if input):    //1 = enable, 0 = hiZ

// PCI/USB Mailbox Registers (DSP IOPAGE=0x00)

#define MBXSTAT        0x20    //  Mailbox Status Mailbox Status

#define MBXCTL         0x22    //  Mailbox Control Mailbox Interrupt Control

#define MBX_IN0        0x24    //  Incoming Mailbox 0 PCI/USB to DSP mailbox

#define MBX_IN1        0x26    //  Incoming Mailbox 1 PCI/USB to DSP mailbox #define MBX_OUT0       0x28    //  Outgoing Mailbox 0 DSP to PCI/USB mailbox

#define MBX_OUT1       0x2A    //  Outgoing Mailbox 0 DSP to PCI/USB mailbox

// SERIAL EEPROM Control Register (DSP IOPAGE=0x00)

#define SPROMCTL 0x30 // Serial EEPROM I/O Control/Status    // Direction and status  for SEN, SCK, SDA pins.

// JTAG ID Registers(DSP IOPAGE=0x00)

#define JTAGIDL 0xA0 // IDCODE[15:0]  JTAG ID0 :    // Value = 0xA1CB ( Read Only ).

#define JTAGIDH 0xA2 // IDCODE[31:16] JTAG ID1 :    // Value = 0x0278 ( Read Only ).

//  AC'97 Control Registers (DSP IOPAGE=0x00)

#define AC97LCTL       0xC0    //  AC'97 Link Control

#define AC97LSTAT      0xC2    //  AC'97 Link Status #define AC97SEN        0xC4    //  AC'97 Slot Enable

#define AC97SVAL       0xC6    //  AC'97 Input Slot Valid

#define AC97SREQ       0xC8    //  AC'97 Slot Request

#define AC97GPIO       0xCA    //  AC'97 External GPIO Register

//  AC'97 External Codec IO Register Spaces

#define AC97CODEC0     0x04    //  External Primary   Codec 0

// IOPAGE space registers (0x00 - 0x7F)

#define AC97CODEC1     0x05    //  External Secondary Codec 1

// IOPAGE space registers (0x00 - 0x7F)

#define AC97CODEC2     0x06    //  External Secondary Codec 2    // IOPAGE space registers (0x00 - 0x7F)

// CardBus Function Event Registers (DSP IOPAGE=0x01)

#define CB_EVENT0       0x00    //  Function 0 Event

#define CB_EVENTMASK0   0x04    //  Function 0 Event Mask

#define CB_PSTATE0      0x08    //  Function 0 Present State #define CB_EVENTFORCE0  0x0C    //  Function 0 Event Force

#define CB_EVENT1       0x10    //  Function 1 Event

#define CB_EVENTMASK1   0x14    //  Function 1 Event Mask

#define CB_PSTATE1      0x18    //  Function 1 Present State #define CB_EVENTFORCE1  0x1C    //  Function 1 Event Force

#define CB_EVENT2       0x20    //  Function 2 Event

#define CB_EVENTMASK2   0x24    //  Function 2 Event Mask

#define CB_PSTATE2      0x28    //  Function 2 Present State #define CB_EVENTFORCE2  0x2C    //  Function 2 Event Force

// PCI DMA Address/Count Registers (DSP IOPAGE=0x08)

#define PCI_Rx0BADDRL   0x00   //  Rx0 DMA Base Address         Bits 15:0 #define PCI_Rx0BADDRH   0x02   //  Rx0 DMA Base Address         Bits 31:16

#define PCI_Rx0CURADDRL 0x04   //  Rx0 DMA Current Address      Bits 15:0

#define PCI_Rx0CURADDRH 0x06   //  Rx0 DMA Current Address      Bits 31:16

#define PCI_Rx0BCNTL    0x08   //  Rx0 DMA Base Count           Bits 15:0

#define PCI_Rx0BCNTH    0x0A   //  Rx0 DMA Base Count           Bits 31:16

#define PCI_Rx0CURCNTL  0x0C   //  Rx0 DMA Current Count        Bits 15:0 #define PCI_Rx0CURCNTH  0x0E   //  Rx0 DMA Current Count        Bits 31:16