The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 5

Register

Name

Description

PCI Address

USB Address

DSP

I/O

Page

DSP

I/O

Address

SYSCON

Chip Mode/Status

0x01-0x00

0x01-0x00

0x00

0x00

PWRCFG0

Function 0 Power Management

0x03-0x02

0x03-0x02

0x00

0x02

PWRCFG1

Function 1 Power Management

0x05-0x04

0x05-0x04

0x00

0x04

PWRCFG2

Function 2 Power Management

0x07-0x06

0x07-0x06

0x00

0x06

PWRP0

DSP 0 Interrupt/Powerdown

0x09-0x08

0x09-0x08

0x00

0x08

PWRP1

DSP 1 Interrupt/Powerdown

0x0B-0x0A

0x0B-0x0A

0x00

0x0A

PLLCTL

DSP PLL Control

0x0D-0x0C

0x0D-0x0C

0x00

0x0C

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit Position

Bit Name

Description

0

RST

Soft Chip Reset.

A write of 1 causes a soft reset to the ADSP-2192. A write of 0 has no effect. Always reads 0. Soft Reset affects the DSPs and the GPIOs. Soft Reset does not affect the PCI, USB, Mailboxes, AC’97, or EEPROM.

Note that the DSP memory pipeline (last 2 writes per bank) is lost upon reset. If desired, it may be flushed by three writes in a row to the same location.

Note: This bit resets to zero.

1

Reserved

Bit Position

Bit Name

Description

2

RDIS

Reset Disable.

When 1, disables a PCI/ISA/CBUS bus reset from affecting any portions of the ADSP-2192 except the bus interface itself. When 0 (default), a bus reset causes the DSPs and AC’97 subsystem to be reset.

Note: If RDIS is set, the DSP can detect that the bus is in reset by the PCIRST bit in the CMSR register. Un-masked Bus Reset affects the DSPs, the GPIOs, the AC’97, and the PCI/USB interface.

Un-masked Bus Reset does not affect the Mailboxes or

EEPROM.

Note that the DSP memory pipeline (last 2 writes per bank) is lost upon reset. If desired, it may be flushed by three writes in a row to the same location.

Note: This bit resets to zero.

3

XON

XTAL Force On.

When 1, causes the XTAL oscillator to run even if all other subsystems are powered down. This permits access to the on-chip control registers when the part is powered down. If the chip and the XTAL oscillator are powered off, attempting to write PDC registers including this one will result in powering up the XTAL and setting the XON bit. The write will succeed, after a delay for the oscillator to stabilize. Subsequent writes or reads should not be attempted until the oscillator has stabilized, about 8K clocks or 333us.

When 0, the XTAL oscillator stops whenever it is not needed by any on-chip subsystem.

Note: This bit resets to zero.