The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 37

//---------------------------------------------------------------------//                     I/O Processor Register Map

//---------------------------------------------------------------------// Chip Control Registers (DSP IOPAGE=0x00)

#define   SYSCON    0x00   // Chip Mode/Status Register

#define   PWRCFG0   0x02   // Function 0 Power Management

#define   PWRCFG1   0x04   // Function 1 Power Management

#define   PWRCFG2   0x06   // Function 2 Power Management #define   PWRP0     0x08   // DSP 0 Interrupt/Power down

#define   PWRP1     0x0A   // DSP 1 Interrupt/Power down

#define   PLLCTL    0x0C   // DSP PLL Control

#define   REVID     0x0E   // ADSP-2192 Revision ID (read only)

//**************************************************

//   SYSCON register

//**************************************************

// Bit Positions

#define SCON_PCIRST_P 15 // PCI Reset

#define SCON_VAUX_P 14 // Vaux Present

#define SCON_PCI_5V_P 13 // PCI 5V level

#define SCON_BUS1_P 11 // Bus Mode

#define SCON_BUS0_P 10 // Bus Mode

#define SCON_CRST1_P 9 // Chip Reset Source

#define SCON_CRST0_P 8 // Chip Reset Source

#define SCON_REGD_P  7  // 2.5V Regulator Control Disable

#define SCON_VXPD_P 6  // Vaux Policy for AC'97 Pad Drivers

#define SCON_VXPW_P 5  // Vaux Policy for AC'97 Pad Well Bias

#define SCON_ACVX_P 4 // AC'97 External Devices Vaux Powered

#define SCON_XON_P 3 // XTAL Force On

#define SCON_RDIS_P 2 // Reset Disable

#define SCON_RST_P 0 // Soft Chip Reset

// Bit Masks

#define SCON_PCIRST    MK_BMSK_(SCON_PCIRST_P) // PCI Reset

#define SCON_VAUX      MK_BMSK_(SCON_VAUX_P  ) // Vaux Present

#define SCON_PCI_5V    MK_BMSK_(SCON_PCI_5V_P) // PCI 5V level #define SCON_BUS1      MK_BMSK_(SCON_BUS1_P  ) // Bus Mode

#define SCON_BUS0      MK_BMSK_(SCON_BUS0_P  ) // Bus Mode

#define SCON_CRST1     MK_BMSK_(SCON_CRST1_P ) // Chip Reset Source

#define SCON_CRST0     MK_BMSK_(SCON_CRST0_P ) // Chip Reset Source

#define SCON_REGD      MK_BMSK_(SCON_REGD_P  ) // 2.5V Regulator

// Control Disable

#define SCON_VXPD MK_BMSK_(SCON_VXPD_P) // Vaux Policy for AC'97

// Pad Drivers

#define SCON_VXPW      MK_BMSK_(SCON_VXPW_P) // Vaux Policy for AC'97

// Pad Well Bias

#define SCON_ACVX      MK_BMSK_(SCON_ACVX_P) // AC'97 External Devices

// Vaux Powered

#define SCON_XON       MK_BMSK_(SCON_XON_P) // XTAL Force On

#define SCON_RDIS      MK_BMSK_(SCON_RDIS_P) // Reset Disable

#define SCON_RST       MK_BMSK_(SCON_RST_P) // Soft Chip Reset

//************************************************** //   PWRPx register

//**************************************************

// Bit Positions

#define PWRP_AINT_P 13  // DSP Interrupt Pending from AC'97 Input #define PWRP_PMINT_P 12  // Power Management Interrupt Pending #define PWRP_GIEN_P 10  // DSP Interrupt Enable for GPIO Input

#define PWRP_GWE_P 6 // DSP Wake up on GPIO Input Enable

#define PWRP_PMWE_P 4  // Power Management Wake up Enable

#define PWRP_RSTD_P 2 // DSP Soft Reset

#define PWRP_PU_P 1 // DSP Power Up

#define PWRP_PD_P 0 // DSP Power Down

// Bit Masks

#define PWRP_AINT     MK_BMSK_(PWRP_AINT_P)   // DSP Interrupt Pending

// from AC'97 Input

#define PWRP_PMINT    MK_BMSK_(PWRP_PMINT_P)   // Power Management

// Interrupt Pending

#define PWRP_GIEN     MK_BMSK_(PWRP_GIEN_P)   // DSP Interrupt Enable    // for GPIO Input

#define PWRP_GWE      MK_BMSK_(PWRP_GWE_P  )   // DSP Wake up on GPIO    // Input Enable

#define PWRP_PMWE     MK_BMSK_(PWRP_PMWE_P )   // Power Management

// Wake up Enable

#define PWRP_RSTD     MK_BMSK_(PWRP_RSTD_P )   // DSP Soft Reset

#define PWRP_PU       MK_BMSK_(PWRP_PU_P   )   // DSP Power Up #define PWRP_PD       MK_BMSK_(PWRP_PD_P   )   // DSP Power Down

//**************************************************

//   PLLCTL register

//**************************************************

// Bit Positions

#define PLLC_DPLLN1_P  11                      // DSP PLL N Divisor Selects

#define PLLC_DPLLN0_P  10                      // DSP PLL N Divisor Selects