The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 6

Bit Position	Bit Name	Description
4	ACVX	AC’97 External Devices Vaux Powered. Controls the AC’97 interface during D3cold (RST asserted). 0 = Disable the interface (drive 0, disable all inputs). This is used if external AC’97 devices are NOT powered during d3cold, and protects the ADSP-2192 from floating inputs and from outputs driving input clamps on an external device. (default) 1 = Interface enabled during RST. Note: This bit resets to zero.
5	Reserved	Reserved
6	Reserved	Reserved
7	REGD	2.5V Regulator Control Disable. Disables the on-chip 2.5V Regulator controller when the 2.5V (IVDD) supply is derived from an external regulator (e.g. in USB and Mini-PCI applications). 0 = On-Chip 2.5V Regulator Control Enabled. (default) 1 = On-Chip 2.5V Regulator Control Disabled. Note: This bit resets to zero.
9:8	CRST<1:0>	Chip Reset Source. Indicates the source of the last reset to the chip (Read-Only) 00 = Power-On Reset 01 = Reserved. 10 = PCI/ISA/CBUS/USB bus interface hard reset 11 = Soft Reset from the CMSR:RST bit Note: the fifth possible reset source, DIP Soft Reset, is indicated by DIP1/2:RD = 1. Each DSP must check its DIP<n>:RD bit and clear it to zero upon reset.

Table B-4. SYSCON Register Bit Descriptions (Continued)

Bit Position	Bit Name	Description
11:10	BUS<1:0>	Bus Mode. Mode Pin status. Sampled at Power-On Reset (Read-Only). 00= PCI 01= CardBus 10= USB 11= Sub-ISA
12	B5V	AC’97 5V level. 1= If the AC’97 interface is powered from nominal 5V; 0 if nominal 3.3V.
13	PCI 5V	PCI 5V level. 1= If the PCI/ISA/CBUS interface is powered from nominal 5V; 0 if nominal 3.3V. Monitors the level of the PCIVDD pins (Read Only).
14	Vaux	Vaux Present. 1= If Vaux is currently powered (Read-Only).
15	PCIRST	PCI Reset. 0= If PCI/CBUS/ISA RST is asserted (which may indicate D3Cold powerdown state). Note: This bit resets to one.

Powe r Ma na g e m e nt Func tions

Power management registers share the same bit specifications. Each register corresponds to one of the PCI functions:

15	14		13:9	8	7	6	5	4	3	2	1	0

! All bits in this register reset to zero.

Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2 Registers

Bit Position	Bit Name	Description
1:0	PWRST<1:0>	PCI Function Power State. Reports this function’s PCI Power Management state from its PMCSR register in PCI Configuration Space. (Read Only)
4:2	Reserved
5	APME	AC’97 Power Management Event Enable. 1= Enables setting this function’s PME bit upon an AC’97 interrupt/wake event. (Read/Write)
6	GPME	GPIO Power Management Event Enable. 1= Enables setting this function’s PME bit upon a GPIO Wakeup event. (Read/Write)
7	Reserved	Reserved
8	PME_EN	Power Management Event Enable. 1= PME_EN bit is set in this function’s PMCSR register in PCI Configuration space.
13:9	Reserved