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The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 2

In the worst case, DSP core P1 posts two AC’97 codec register writes just after the start of a new Frame. DSP core P0 immediately follows with a read to an AC’97 codec register. DSP core P0 will be unable to compute, DMA, or interrupt for 87.89 µs. DSP core P1 can compute with data in its own memory, but cannot communicate with DSP core P0 or access any PDC bus register for 87.89 µs. The external bus interface can communicate with DSP core P1, but cannot communicate with DSP core P0 or access any PDC bus register for 87.89 µs. In the state, the entire ADSP-2192 system is highly constrained.

A DSP-2192 Sy ste m C ontrol Re g iste rs

The following tables show the System Control Registers in each DSP core.

Table B-1. ADSP-2192 System Control Registers

Address	Register	Function
00	B0	Base Register0
01	B1	Base Register1
02	B2	Base Register2
03	B3	Base Register3
04	B4	Base Register4
05	B5	Base Register5
06	B6	Base Register6
07	B7	Base Register7
08 - 0B		Reserved
0C	DMAPAGE	DMA Page Register
0D - 0E		Reserved
0F	CACTL	Cache Control Register
10	STCTL0	FIFO0 Transmit Control Register
11	SRCTL0	FIFO0 Receive Control Register
12	TX0	FIFO0 Transmit Data (TX) register
13	RX0	FIFO0 Receive Data (RX) register

Table B-1. ADSP-2192 System Control Registers (Continued)

Address	Register	Function
14 - 1F		Reserved
20	STCTL1	FIFO1 Transmit Control Register
21	SRCTL1	FIFO1 Receive Control Register
22	TX1	FIFO1 Transmit Data (TX) register
23	RX1	FIFO1 Receive Data (RX) register
24 - 2F		Reserved
30	TPERIOD	Timer Period Register
31	TCOUNT	Timer Counter Register
32	TSCALE	Timer Scaling Register
33	TSCALECNT	Timer Scale Count Register
34	FLAGS	Flags Register
35 - 3F		Reserved
40 - 43		Reserved
44	MASTADDR	DMA Address, DSP Master DMA
45	MASTNXTADDR	DMA Next Address, DSP Master DMA
46	MASTCNT	DMA Count, DSP Master DMA
47	MASTCURCNT	DMA Current Count, DSP Master DMA
48	TX0ADDR	DMA Address, FIFO0 Transmit
49	TX0NXTADDR	DMA Next Address, FIFO0 Transmit

Table B-1. ADSP-2192 System Control Registers (Continued)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

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