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The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 21

PC I C onfig ura tion Re g iste r Sp a c e , Func tion 0

PCI Configuration Spaces should only be accessed by the DSP, and only during the boot process. After the PCI interface has been configured, bit 2 of the PCI_CFGCTL register (ConfRdy) should be set by the DSP. This allows the PCI interface access to these registers while at the same time denying the DSP access.

!

Access to these registers is controlled by the PCI RDY bit in the Chip Mode/Status Register (Page 0x00, Address 0x00).

Table B-25. Function 0 Registers

Register Name

Description

PCI Address

USB Address

DSP

I/O

Page

DSP

I/O

Address

PCI_CFG0_VID

Config0 Vendor

ID    

0x01-0x00

n/a

0x09

0x00

PCI_CFG0_DID

Config0 Device ID    

0x03-0x02

n/a

0x09

0x02

Table B-25. Function 0 Registers  (Continued)

Register Name

Description

PCI Address

USB Address

DSP

I/O

Page

DSP

I/O

Address

PCI_CFG0_CCODEL

Config0 Class

Code[7:0],Rev

ID    

0x08

n/a

0x09

0x08

PCI_CFG0_CCODEH

Config0 Class Code[23:8]    

0x0B-0x0A

n/a

0x09

0x0A

PCI_CFG0_SVID

Config0 Subsystem Vendor ID    

0x2D-0x2C

n/a

0x09

0x2C

PCI_CFG0_SDID

Config0 Subsystem Device

ID

0x2F-0x2E

n/a

0x09

0x2E

PCI_CFG0_PWRMT

Config0 Power Mgt Capabilities.

Bit 15 set if Vaux is sensed valid.    

0x45-0x44

n/a

0x09

0x44

PC I C onfig ura tion Re g iste r Sp a c e , Func tion 1

PCI Configuration Spaces should be accessed only by the DSP, and only during the boot process. After the PCI interface has been configured, bit 2 of the PCI_CFGCTL register (ConfRdy) should be set by the DSP. This allows the PCI interface access to these registers while at the same time denying the DSP access.

!

Access to these registers is controlled by the PCI RDY bit in the Chip Mode/Status Register (Page 0x00, Address 0x00). See “ADSP-2192 Chip Control Registers” on page B-13.

Table B-26. Function 1 Registers

Register Name

Description

PCI Address

USB Address

DSP

I/O

Page

DSP

I/O

Address

PCI_CFG1_VID

Config1 Vendor ID

0x01-0x00

n/a

0x0A

0x00

PCI_CFG1_DID

Config1 Device ID

0x03-0x02

n/a

0x0A

0x02

PCI_CFG1_CCODEL

Config1 Class

Code[7:0], Rev

ID

0x08

n/a

0x0A

0x08

PCI_CFG1_CCODEH

Config1 Class Code[23:8]

0x0B-0x0A

n/a

0x0A

0x0A

PCI_CFG1_SVID

Config1 Subsystem Vendor ID

0x2D-0x2C

n/a

0x0A

0x2C

PCI_CFG1_SDID

Config1 Subsystem Device ID

0x2F-0x2E

n/a

0x0A

0x2E

Table B-26. Function 1 Registers (Continued)

Register Name

Description

PCI Address

USB Address

DSP

I/O

Page

DSP

I/O

Address

PCI_CFG1_PWRMT

Config1 Power

Mgt Capabilities

Bit 15 set, if

Vaux is sensed valid.

0x45-0x44

n/a

0x0A

0x44
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