The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 14

Bit Position

Bit Name

Description

15

INTM

Interrupt / Wakeup Mask.

Enables assertion of INTA and PME//CSTSCHG when in Card

Bus mode (CBUS = low). Has no effect upon INTA or PME/CSTSCHG when not in CardBus mode.

In CardBus mode: INTA is asserted when: CB_FEM0:INTM=1 and CB_FE0:INTR=1.

CSTSCHG is asserted high when: CB_FEM0:INTRM=1 and

CB_FEM0:WKUP=1 and CB_FEM0:GWKM=1 and

CB_FE0:GWKE=1. This bit is cleared by power-on reset and

PCI RST. It is not affected by SYSRST or Soft Reset.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit Position

Bit Name

Description

3:0

Reserved

4

GWAKE

Current wakeup state.

This bit reflects the current state of the wakeup condition from either AC’97 or the local GPIOs, if enabled by ACPU or

GPU.

14:5

Reserved

Bit Position

Bit Name

Description

15

INTR

Current Interrupt State.

This bit reflects the combined state of the current interrupt inputs to DSPI, WKI, GPI, and TABI.

Register Name

Description

PCI Address

USB Address

DSP

I/O

Page

DSP

I/O

Address

CBEVENT0

Function 0 Event

0x103-0x100

n/a

0x01

0x00

CBEVENT_MSK0

Function 0 Event

Mask

0x107-0x104

n/a

0x01

0x04

CBPRES_STATE0

Function 0 Present

State

0x10B-0x108

n/a

0x01

0x08

CBEVENT_FORCE0

Function 0 Event

Force

0x10F-0x10C

n/a

0x01

0x0C

CBEVENT1

Function 1 Event

0x113-0x110

n/a

0x01

0x10

CBEVENT_MSK1

Function 1 Event

Mask

0x117-0x114

n/a

0x01

0x14

CBPRES_STATE1

Function 1 Present

State

0x11B-0x118

n/a

0x01

0x18

CBEVENT_FORCE1

Function 1 Event

Force

0x11F-0x11C

n/a

0x01

0x1C

CBEVENT2

Function 2 Event

0x123-0x120

n/a

0x01

0x20

CBEVENT_MSK2

Function 2 Event

Mask

0x127-0x124

n/a

0x01

0x24

Register Name

Description

PCI Address

USB Address

DSP

I/O

Page

DSP

I/O

Address

CBPRES_STATE2

Function 2 Present

State

0x12B-0x128

n/a

0x01

0x28

CBEVENT_FORCE2

Function 2 Event

Force

0x12F-0x12C

n/a

0x01

0x2C