The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 36

//---------------------------------------------------------------------//                System Register bit definitions                            //---------------------------------------------------------------------//************************************************** //   IRPTL and IMASK registers

//**************************************************

// Bit Positions

#define INT_MAILBXI_P 4 // Bit  4: Offset: 10: Mailbox

#define INT_TMZHI_P  5 // Bit  5: Offset: 14: Timer (High Priority)

#define INT_INT6_P 6 // Bit  6: Offset: 18: Unused #define INT_PCIBMI_P 7 // Bit  7: Offset: 1c: PCI

#define INT_DSPDSPI_P 8 // Bit  8: Offset: 20: DSP

#define INT_FIFO0TXI_P 9  // Bit  9: Offset: 24: FIFO 0 Transmit Empty #define INT_FIFO0RXI_P 10  // Bit 10: Offset: 28: FIFO 0 Receive Full #define INT_FIFO1TXI_P 11  // Bit 11: Offset: 2c: FIFO 1 Transmit Empty #define INT_FIFO1RXI_P 12  // Bit 12: Offset: 30: FIFO 1 Receive Full

#define INT_INT13_P 13 // Bit 13: Offset: 34: Unused

#define INT_INT14_P 14 // Bit 14: Offset: 38: Unused

#define INT_AC97FR_P 15 // Bit 15: Offset: 3c: AC97 serial port

// Bit Masks

#define INT_MAILBXI MK_BMSK_(INT_MAILBXI_P) // Offset: 10: Mailbox

#define INT_TMZHI MK_BMSK_(INT_TMZHI_P) // Offset: 14: Timer

// (High Priority)

#define INT_INT6 MK_BMSK_(INT_INT6_P) // Offset: 18: Unused

#define INT_PCIBMI MK_BMSK_(INT_PCIBMI_P) // Offset: 1c: PCI

#define INT_DSPDSPI MK_BMSK_(INT_DSPDSPI_P) // Offset: 20: DSP #define INT_FIFO0TXI MK_BMSK_(INT_FIFO0TXI_P) // Offset: 24:    // FIFO 0 Transmit Empty

#define INT_FIFO0RXI MK_BMSK_(INT_FIFO0RXI_P) // Offset: 28:

// FIFO 0 Receive Full

#define INT_FIFO1TXI MK_BMSK_(INT_FIFO1TXI_P) // Offset: 2c:    // FIFO 1 Transmit Empty

#define INT_FIFO1RXI MK_BMSK_(INT_FIFO1RXI_P) // Offset: 30:

// FIFO 1 Receive Full

#define INT_INT13 MK_BMSK_(INT_INT13_P) // Offset: 34: Unused

#define INT_INT14  MK_BMSK_(INT_INT14_P) // Offset: 38: Unused #defineI NT_AC97FR MK_BMSK_(INT_AC97FR_P)/ / Offset:3 c: AC97s erial port

//**************************************************

//   SRCTLx and STCTLx registers

//**************************************************

// Bit Positions

#define SCTL_SPEN_P     0                      // AC'97 FIFO Connection Enable

#define SCTL_SSEL3_P    7                      // AC'97 Slot Select

#define SCTL_SSEL2_P    6                      // AC'97 Slot Select

#define SCTL_SSEL1_P    5                      // AC'97 Slot Select

#define SCTL_SSEL0_P    4                      // AC'97 Slot Select

#define SCTL_FIP2_P    10                      // AC'97 FIFO Interrupt Position #define SCTL_FIP1_P     9                      // AC'97 FIFO Interrupt Position

#define SCTL_FIP0_P     8                      // AC'97 FIFO Interrupt Position

#define SCTL_SDEN_P    11                      // AC'97 Port DMA Enable #define SCTL_FULL_P    13                      // FIFO Full, (read-only)

#define SCTL_EMPTY_P   14                      // FIFO Empty, (read-only) #define SCTL_FLOW_P    15                      // FIFO Over/Underflow, sticky, write-one-clear)

// Bit Masks

#defineS CTL_SPEN MK_BMSK_(SCTL_SPEN_P)/ / AC'97F IFO ConnectionE nable

#define SCTL_SSEL3 MK_BMSK_(SCTL_SSEL3_P) // AC'97 Slot Select #define SCTL_SSEL2 MK_BMSK_(SCTL_SSEL2_P) // AC'97 Slot Select

#define SCTL_SSEL1 MK_BMSK_(SCTL_SSEL1_P) // AC'97 Slot Select

#define SCTL_SSEL0 MK_BMSK_(SCTL_SSEL0_P) // AC'97 Slot Select

#defineS CTL_FIP2 MK_BMSK_(SCTL_FIP2_P)  //A C'97    FIFOI nterrupt Position #defineS CTL_FIP1 MK_BMSK_(SCTL_FIP1_P)  //A C'97    FIFOI nterrupt Position

#defineS CTL_FIP0 MK_BMSK_(SCTL_FIP0_P)  //A C'97  FIFOI nterrupt Position

#define SCTL_SDEN MK_BMSK_(SCTL_SDEN_P )  // AC'97 Port DMA Enable #define SCTL_FULL MK_BMSK_(SCTL_FULL_P )  // FIFO Full, read-only

#define SCTL_EMPTY MK_BMSK_(SCTL_EMPTY_P)  // FIFO Empty, read-only

#defineS CTL_FLOW MK_BMSK_(SCTL_FLOW_P)//F IFO   Over/Underflow,s ticky,    // write-one-clear