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The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 31

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NK

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TB3

TB2

TB1

ST3

ST2

ST1

FE

Figure B-8. USB Endpoint Stall Policy Register

Contains the base NAK count and FIFO error policy bits for Endpoints 4-11. The STALL status and Data toggle bits for Endpoints 1-3 are included as well. This register is read/write by the MCU only.      

Table B-41. USB Endpoint Stall Policy Register

ST[3:1]

A value of 1 means the Endpoint is stalled. ST[1] maps to Endpoint 1, ST[2] maps to Endpoint 2, etc.

TB[3:1]

Toggle bit for Endpoint. Reflects the current state of the DATA toggle bit. ST[1] maps to Endpoint 1, ST[2] maps to Endpoint 2, etc.

NK[3:0]

Base NAK counter. Determines how many sequential NAKs are issued before sending zero length packet, or a packet less than the maximum packet size, on any given Endpoint.

FE

FIFO error policy. A value of 1 means: Endpoint FIFO is overrun/underrun, STALL Endpoint

USB Endpoint 1 Code Download Base Address Register

LSW

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MSW

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DS

AD

Figure B-9. USB Endpoint 1 Code Download Base Address Register

Contains an 18 bit address which corresponds to the starting location for

DSP code download on Endpoint 1. This register is read/write by the MCU only. The most significant bit (DS bit) selects either DSP1 PM address space (DS=0) or DSP2 PM address space (DS=1).

USB Endpoint 2 Code Download Base Address Register

LSW

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MSW

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