The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 12

Of the four function modes, PCI, USB, sub-ISA, and Cardbus, these function event registers are used only in CardBus mode to provide status registers for power management.

In a CardBus system (specified by BUSMODE=01), the operating system handles Power Management in one of two ways. If the O/S is

ACPI-compliant, the OS uses the Power Management registers in PCI Configuration space in the normal fashion. If the O/S is an older legacy system, it looks for a set of four 32-bit Function Event registers, one set per card function. (The upper 16 bits of each register are reserved and are implemented as read-only with 0s.) These registers are used only in CardBus systems, and have no effect on operation when the ADSP-2192 is not in CardBus mode (BUSMODE=01). The registers for each of the three functions are largely independent.

The CardBus Function Event registers contain bits similar to those in the PCI Power Management registers:

•  Function Event Register GWAKE-E == PCI PME_Status

•  Function Event Mask register GWAKE-M == PCI PME_Enable In addition, the CardBus registers define the following:

•  Interrupt Mask INTR M - global mask bit for both interrupt and wakeup (PME) signalling

•  Wakeup Mask WKUPM - additional PCI PME_Enable

•  Event Force bits for interrupt (INTRF) and wakeup (GWAKEF) for software development

The CardBus Function Event registers are defined to inter-operate with the PCI Power Management Control/Status (SYSCON) register as follows:

•  PCI updates PME_EN bit.

CardBus GWAKM and WKUPM take the new value.

•  PCI clears PME_Status (writes 1).

CardBus GWAKE is cleared.

•  CardBus updates GWAKM or WKUP.

No effect in PCI PMCSR.

•  CardBus clears GWAKE_E (writes 1).

PCI PME_Status bit is cleared.

•  Power Management event occurs.

Both GWAKE and PME_Status are set; PME may assert.

•  Host Interrupt occurs.

INTRE is set, INTA may assert.

C STSC HG Sig na l

In CardBus systems, power management events are signaled to the host by an active-high signal called CSTSCHG. An external FET or inverter is used with the ADSP-2192’s active-low PME signal to create CSTSCHG. In CardBus mode, PME is asserted under the following conditions:

•  The function’s INTRM master interrupt/wakeup mask bit is 1

•  The function’s WKUPM master wakeup mask bit is 1

•  The function’s GWAKEM general wakeup bit is 1

•  The function’s GWAKEE general-wake event pending bit is 1

GWAKE is an alias of the function’s SYSCON:PME_Status latch. GWAKEE is set to 1 when any of the conditions occurs which would set PME_Status for that function, according to the masks in the function’s Function Power Management register (PWRCFG0/1/2). In addition, writing a 1 to the GWAKE_F bit in the function’s Function Event Force register sets the GWAKEE bit (and PME_Status bit) for that function to 1.

INTA Sig na l

In CardBus systems, assertion of the INTA pin is controlled by the INTRM master interrupt mask bit, in addition to the other interrupt control registers on the ADSP-2192. The INTR_E bit indicates if an interrupt is pending. The INTA pin is asserted under the following conditions:

•  The function’s INTRM master interrupt/wakeup mask bit is 1

•  The function’s INTRE interrupt pending bit is 1

INTRE is set when any of the conditions occurs which would cause INTA to be asserted in PCI systems, according to the settings in the PCI Interrupt Register. All three functions are controlled by the same interrupt-detect signal. Additionally, writing a 1 to the INTRF bit in a function’s Function Event Force register sets that function’s INTRE bit and, if the corresponding INTRM bit is set, the INTA pin is asserted. Writing INTRF directly is the only way for an individual function to set its INTRE bit and hence signal an interrupt independently of the other functions.