|
Name |
Comments |
||
|
SERR# Enable |
8 |
If any function enables SERR driver, then
SERR may be asserted |
|
|
Fast Back-to-back Enable |
9 |
No function generates fast back-to-back transactions |
|
|
Status Register Bits |
Capabilities List |
4 |
Read-only |
|
66 MHz Capable |
5 |
Read-only |
|
|
Reserved |
6 |
Read-only |
|
|
Fast Back-to-back Capable |
7 |
Read-only. |
|
|
Master Data Parity Error |
8 |
Separate for each function, no interaction |
|
|
DEVSEL Timing |
10-9 |
Read-only |
|
|
Signaled Target Abort |
11 |
Separate for each function, no interaction |
|
|
Received Target Abort |
12 |
Separate for each function, no interaction |
|
|
Received Master Abort |
13 |
Separate for each function, no interaction |
|
|
Signaled System Error |
14 |
Separate for each function, set if SERR
enabled and SERR asserted |
|
|
Detected Parity Error |
15 |
Separate for each function, but set in all functions simultaneously |
|
Table B-31. Configuration Space Register Interactions Between Functions (Continued)
|
Name |
Comments |
|
Revision ID |
Read-only |
|
Class Code |
Separate registers, no interaction |
|
Cache Line Size |
Read-only |
|
Latency Timer |
Separate for each function, no interaction |
|
Header Type |
Read-only |
|
Base Address 1 |
In range signal ORed between functions, any function can access memory |
|
Base Address 2 |
In range signal ORed between functions, any function can access memory |
|
Base Address 3 |
In range signal ORed between functions, any function can access memory |
|
Base Address 4 |
In range signal ORed between functions, any function can access memory |
|
Subsystem Vendor ID |
Separate registers, no interaction |
|
Subsystem Device ID |
Separate registers, no interaction |
|
Capabilities Pointer |
Read-only |
|
Interrupt Line |
Separate registers, no interaction |
|
Interrupt Pin |
Read-only |
|
Min_Gnt |
Read-only. |
|
Max_Lat |
Read-only |
Table B-32. Power Management Register Interactions Between Functions
|
Name |
Comments |
||
|
Capability ID |
Read-only |
||
|
Next_Cap_Ptr |
Read-only |
||
|
Power Management Capabilities Bits |
Version |
2-0 |
Read-only |
|
PME Clock |
3 |
Read-only |
|
|
Reserved |
4 |
Read-only |
|
|
Device Specific Initialization |
5 |
Read-only |
|
|
Aux Current |
8-6 |
Read-only by PCI, writable by DSP |
|
|
D1 Support |
9 |
Read-only |
|
|
D2 Support |
10 |
Read-only |
|
|
PME Support |
15-11 |
Read-only by PCI, writable by DSP |
|
|
Power Management Control/ Status Bits |
Power State |
1-0 |
Part will be in highest power state of the three functions |
|
Reserved |
7-2 |
Read-only, no interaction |
|
|
PME Enable |
8 |
Separate for each function, no interaction |
|
|
Data Select |
12-9 |
Read-only, no interaction |
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