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The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 13

C IS Tup le Re q uire m e nts

!

The four Function Event Registers for each function are pointed to by a data structure in CIS (Card Information Services) RAM, which must be initialized by the DSP from ROM at power-up. A CISTPL_CONFIG_CB CIS tuple must be provided for each function to point to the function event registers in BAR1 at the appropriate offset:

Table B-11. CIS Tuple Requirements

Function

Value of TPCC_ADDR in CISTPL_CONFIG_CB

Meaning

0

0x0000_0101

Offset 0x0000_0100 within BAR 1

1

10x0000_0111

Offset 0x0000_0110 within BAR 1

2

0x0000_0121

Offset 0x0000_0120 within BAR 1

CardBus Function Event (CB_FE0) Register

! All bits in this register are reset to zero.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Table B-12. CB_FE0 Register Bit Description

Bit Position

Bit Name

Description

3:0

Reserved

4

GWKE

General Wakeup Event Pending.

This bit is equivalent to the PME_Status bit. It reads 1 if CB_FPS0:GWAKE has been set by either a wakeup event on AC’97 as enabled by APME, or by a wakeup event on GPIOs enabled by GPME.

A write of a 1 clears this bit. This nonvolatile bit is reset by

power-on reset only, and is not affected by PCI RST, SYSRST or Soft Reset.

14:5

Reserved

15

INTE

Interrupt Event Pending.

Reads 1 if CB_FPS0:INTR is set and CB_FEM0:INTRM is 1. Default=0.

A write of 1 clears all of the interrupts DSPI, WKI, GPI, and TABI corresponding to bits 15:12 of the PCS register. This bit is cleared by power-on reset and PCI RST. It is not affected

by SYSRST or the Soft Reset bit PCC:RST.

CardBus Function Event Mask (CB_FEM0) Register ! All bits in this register are reset to zero.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Table B-13. CB_FEM0 Register Bit Descriptions

Bit Position

Bit Name

Description

3:0

Reserved

4

GWKM

General Wakeup Mask.

This bit is equivalent to PME_Enable. Enables assertion of CSTSCHG in Cardbus mode (see above).

5

Reserved

6

Reserved

13:7

Reserved

14

WKUP

Wakeup Enable.

Master wakeup enable for assertion of CSTSCHG/PME when in CardBus mode. When not in CardBus mode, this has no effect. This nonvolatile bit is reset by power-on reset only,

and is not affected by PCI RST, SYSRST or Soft Reset.

Table B-13. CB_FEM0 Register Bit Descriptions  (Continued)

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