The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 20

Table B-24. PCI_CFGCTL Register Bit Descriptions  (Continued)

PCI Configuration Register Space

The ADSP-2192 PCI Interface requires separate configuration space for each function due to operating system requirements. This section describes the registers in each function, their reset conditions, and interaction between the functions to access and control the ADSP-2192 hardware.

C om m ona litie s Be twe e n the Thre e Func tions

Each function contains a complete set of registers in the predefined header region, as defined in PCI Local Bus Specification, Revision 2.2. In addition, each function contains optional registers to support PCI Bus Power Management. Registers that are unimplemented or read-only in one function are similarly defined in the other functions.

Each function contains four base address registers that access ADSP-2192 control registers and DSP memory. Base address register (BAR1) accesses the ADSP-2192 control registers. Accesses to the control registers via BAR1 use PCI memory accesses. BAR1 requests a memory allocation of 1024 bytes. Access to DSP memory occurs via BAR2 and BAR3. BAR2 is accesses 24-bit DSP memory (i.e. for DSP program downloading) and BAR3 accesses 16-bit DSP memory. BAR4 provides I/O space access to both the control registers and the DSP memory.

The configuration space headers are defined by Function 0 (register information shown in Table B-28 on page B-60), Function 1 (register information shown in Table B-29 on page B-63), and Function 2 (register information shown in Table B-30 on page B-65).

Each function is defined by writing to the class code register of that function during bootup. Additionally, during boot time, the DSP will have the possibility of disabling one or more of the functions. If only two functions are enabled, they will be functions zero and one. If only one function is enabled, it will be function zero.

Inte ra c tions Be twe e n the Thre e Func tions

Because all functions access and control a single set of resources, potential conflicts occur in the control specified by the configuration. For each of the potential conflicts, a resolution is proposed. Table B-31 on page B-67 and Table B-32 on page B-70 identify the proposed resolutions (interactions). Table B-31 covers the registers in the predefined header space and Table B-32 covers the Power Management registers.

Target accesses to registers and DSP memory can go through any function. As long as the Memory Space access enable bit is set in that function, then PCI memory accesses whose address matches the locations programmed into a function’s BARs 1-3 will be able to read or write any visible register or memory location within the ADSP-2192. Similarly, if I/O Space access enable is set, then PCI I/O accesses can be performed via BAR4.

Within the Power Management section of the configuration blocks, there are a few interactions. The part will stay in the highest power state between the three functions. Thus if a modem is requested to be powered down to state D2, but Function 0 is set for power state D0, the overall chip will remain in state D0. When one or the other of the functions is in a low power state, they can only respond to configuration accesses, regardless of the power state of the other functions. Similarly, when a function transitions from D3hot to D0, that function’s configuration space will be re-initialized. Each function has a separate PME enable and PME status bit. Whenever possible, the hardware will identify Functio n0 wakeup from wakeup and set the appropriate PME status. When no determination is possible, both PME status bits will be set.