15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
G PIO Wa k e up C ontrol (G PIO WA KEC TL) Re g iste r ! This register resets to zero.
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
G PIO Sta tus (G PIO STA T) Re g iste r ! This register resets to 0xFF.
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
G PIO C ontrol (G PIO C TL) Re g iste r ! This register resets to 0x7F.
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
G PIO Pullup (G PIO PUP) Re g iste r ! This register resets to 0xFF.
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
G PIO Pulld own (G PIO PDN) Re g iste r ! This register resets to zero. |
|||||||||||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
The EEPROM register controls access to the serial EEPROM. Table B-8 lists the Peripheral Device Control Register Space for EEPROM Control Register.
Table B-8. SPROMCTL Control Register
Register Name |
Description |
PCI Address |
USB Address |
DSP I/O Page |
DSP I/O Address |
SPROMCTL |
EEPROM I/O Control/Status Controls the direction and status for SEN, SCK, SDA pins. |
0x30 |
0x30 |
0x00 |
0x30 |
This register is reset by any of the following:
• Power-On Reset
• SYSRST asserted
• Soft Reset using the PCC:RST bit
• PCI RST asserted when the AC97LCTL:DSPR bit is 0
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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