The DSP has general-purpose and dedicated registers in each of its functional blocks, страница 18

DMA Tra nsfe r C ount 1 - Bus Ma ste r Sa m p le Tra nsfe r C ount

(PC I_MSTRC NT1) Re g iste r

This 16-bit register contains a count of the number of words to be transferred between PCI address space and the DSP internal memory.

! All bits in this register reset to 0.

DMA Control X - Bus Master Control and Status (PCI_DMACx) Re g iste r

! All bits in this register reset to 0.

Table B-22. PCI_DMACx Register Bit Descriptions

Table B-22. PCI_DMACx Register Bit Descriptions  (Continued)

PC I Inte rrup t (PC I_IRQ STA T) Re g iste r

There are a variety of potential sources of interrupts to the PCI host besides the bus master DMA interrupts. A single interrupt pin, INTA, is signals these interrupts back to the host. The PCI Interrupt Register consolidates all of the possible interrupt sources; the bits of this register are shown in Table B-28 on page B-60. The register bits are set by the various sources and can be cleared by writing a 1 to the bits to be cleared.

Interrupts may be sensitive either to edges or levels, as indicated in Table B-28. In particular, the PCI GPIO interrupt is level sensitive, and is asserted when any of the GPIO’s individual sticky status bits is true. If an interrupt service routine is in the process of acknowledging one GPIO interrupt (by clearing its sticky status and then writing a 1 to

PCI_IRQSTAT:GPIO) while an event occurs on another GPIO, it is possible for the ISR to miss the second event, should it occur between the time the ISR reads the GPIOs’ status and when the ISR clears the PCI_IRQSTAT:GPIO bit. The GPIO interrupt is level sensitive to accommodate this case; the

PCI_IRQSTAT:GPIO interrupt bit and the INTA pin immediately reassert after clearing. The ISR may be written in two ways to detect this case: it may either exit and be immediately re-triggered, or it may read back the PCI_IRQSTAT register after the clear to see if any bit has been set again indicating the occurrence of some new interrupt.

Status bits for all possible PCI interrupt sources (read/write-1-clear).

! All bits in this register reset to 0.