#define PLLC_DPLLK1_P 9 // DSP PLL K Divisor Selects
#define PLLC_DPLLK0_P 8 // DSP PLL K Divisor Selects
#define PLLC_DPLLM3_P 7 // DSP PLL M Divisor Selects
#define PLLC_DPLLM2_P 6 // DSP PLL M Divisor Selects
#define PLLC_DPLLM1_P 5 // DSP PLL M Divisor Selects
#define PLLC_DPLLM0_P 4 // DSP PLL M Divisor Selects
#define PLLC_DADJ_P 0 // DSP PLL Adjust
// Bit Masks
#defineP LLC_DPLLN1 MK_BMSK_(PLLC_DPLLN1_P)/ / DSPP LL ND ivisor Selects
#defineP LLC_DPLLN0 MK_BMSK_(PLLC_DPLLN0_P)/ / DSPP LL ND ivisor Selects
#defineP LLC_DPLLK1 MK_BMSK_(PLLC_DPLLK1_P)/ / DSPP LL KD ivisor Selects
#defineP LLC_DPLLK0 MK_BMSK_(PLLC_DPLLK0_P)/ / DSPP LL KD ivisor Selects
#defineP LLC_DPLLM3 MK_BMSK_(PLLC_DPLLM3_P)/ / DSPP LL MD ivisor Selects
#defineP LLC_DPLLM2 MK_BMSK_(PLLC_DPLLM2_P)/ / DSPP LL MD ivisor Selects
#defineP LLC_DPLLM1 MK_BMSK_(PLLC_DPLLM1_P)/ / DSPP LL MD ivisor Selects
#defineP LLC_DPLLM0 MK_BMSK_(PLLC_DPLLM0_P)/ / DSPP LL MD ivisor Selects
#define PLLC_DADJ MK_BMSK_(PLLC_DADJ_P) // DSP PLL Adjust
//**************************************************
// PWRCFGx register
//**************************************************
// Bit Positions
#define PWRC_SPME_P 14 // Power Management Event Set
#define PWRC_GPME_P 6 // GPIO Power Management Event Enable
#define PWRC_PWRST1_P 1 // PCI Function Power State
#define PWRC_PWRST0_P 0 // PCI Function Power State
// Bit Masks
#define PWRC_SPME MK_BMSK_(PWRC_SPME_P) // DSP PLL N Divisor Selects
#define PWRC_GPME MK_BMSK_(PWRC_GPME_P) // DSP PLL N Divisor Selects #defineP WRC_PWRST1 MK_BMSK_(PWRC_PWRST1_P)/ / DSPP LL KD ivisor Selects
#defineP WRC_PWRST0 MK_BMSK_(PWRC_PWRST0_P)/ / DSPP LL KD ivisor Selects
//---------------------------------------------------------------------// System Register address definitions //---------------------------------------------------------------------#define DMAPAGE 0x0C // DMA Page Register
#define STCTL0 0x10 // FIFO0 Transmit Control Register #define SRCTL0 0x11 // FIFO0 Receive Control Register
#define TX0 0x12 // FIFO0 Transmit Data (TX) register
#define RX0 0x13 // FIFO0 Receive Data (RX) register
#define STCTL1 0x20 // FIFO1 Transmit Control Register #define SRCTL1 0x21 // FIFO1 Receive Control Register
#define TX1 0x22 // FIFO1 Transmit Data (TX) register
#define RX1 0x23 // FIFO1 Receive Data (RX) register
#define TPERIOD 0x30 // Timer Period Register
#define TCOUNT 0x31 // Timer Counter Register
#define TSCALE 0x32 // Timer Scaling Register
#define TSCALECNT 0x33 // Timer Scale Count Register
#define FLAGS 0x34 // Flags Register
#define MASTADDR 0x44 // DMA Address, DSP Master DMA
#define MASTNXTADDR 0x45 // DMA Next Address, DSP Master DMA #define MASTCNT 0x46 // DMA Count, DSP Master DMA #define MASTCURCNT 0x47 // DMA Current Count, DSP Master DMA
#define TX0ADDR 0x48 // DMA Address, Fifo0 Transmit
#define TX0NXTADDR 0x49 // DMA Next Address, Fifo0 Transmit
#define TX0CNT 0x4A // DMA Count, Fifo0 Transmit
#define TX0CURCNT 0x4B // DMA Current Count, Fifo0 Transmit
#define RX0ADDR 0x4C // DMA Address, Fifo0 Receive
#define RX0NXTADDR 0x4D // DMA Next Address, Fifo0 Receive #define RX0CNT 0x4E // DMA Count, Fifo0 Receive #define RX0CURCNT 0x4F // DMA Current Count, Fifo0 Receive #define TX1ADDR 0x50 // DMA Address, Fifo1 Transmit
#define TX1NXTADDR 0x51 // DMA Next Address, Fifo1 Transmit #define TX1CNT 0x52 // DMA Count, Fifo1 Transmit
#define TX1CURCNT 0x53 // DMA Current Count, Fifo1 Transmit
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