Address |
Name |
Comment |
0x101C-0x101D |
USB EP11 Description |
Configures Endpoint |
0x101E-0x101F |
USB EP11 NAK Counter |
|
0x1020-0x1021 |
USB EP STALL Policy |
|
0x1040-0x1043 |
USB EP1 Code Download Base Address |
Starting address for code download on Endpoint 1 |
0x1044-0x1047 |
USB EP2 Code Download Base Address |
Starting address for code download on Endpoint 2 |
0x1048-0x104B |
USB EP3 Code Download Base Address |
Starting address for code download on Endpoint 3 |
0x1060-0x1063 |
USB EP1 Code Current Write Pointer Offset |
Current write pointer offset for code download on Endpoint 1 |
0x1064-0x1067 |
USB EP2 Code Current Write Pointer Offset |
Current write pointer offset for code download on Endpoint 2 |
0x1068-0x106B |
USB EP3 Code Current Write Pointer Offset |
Current write pointer offset for code download on Endpoint 3 |
0x2000-0x2001 |
USB Register I/O Address |
|
0x2002-0x2003 |
USB Register I/O Data |
|
0x3000-0x3FFF |
USB MCU Program Mem |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
TB |
LT |
LT |
TY |
TY |
DR |
PS |
PS |
PS |
PS |
PS |
PS |
PS |
PS |
PS |
PS |
Figure B-6. USB Endpoint Description Register
Provides the USB core with information about the Endpoint type, direction, and maximum packet size. This register is read/write by the MCU only. This register is defined for Endpoints[4:11].
Table B-39. USB Endpoint Description Register
PS[9:0] |
Maximum packet size for Endpoint |
LT[1:0] |
Last transaction handshake indicator bits sent by the ADSP-2192: 00 = Clear 01 = ACK 10 = NAK 11 = ERR |
TY[1:0] |
Endpoint type bits: 00 = DISABLED 01 = ISO 10 = Bulk 11 = Interrupt |
DR |
Endpoint direction bit: 1 = IN 0 = OUT |
TB |
Toggle bit for Endpoint. Reflects the current state of the DATA toggle bit. |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
X |
X |
X |
X |
X |
X |
X |
X |
X |
X |
NE |
ST |
NC |
NC |
NC |
NC |
Figure B-7. USB Endpoint NAK Counter Register
Contains the individual NAK count, stall control, and NAK counter enable bits for Endpoints 4-11. This register is read/write by the MCU only.
Table B-40. USB Endpoint NAK Counter Register
NC[3:0] |
NAK counter. Number of sequential NAKs that have occurred on a given Endpoint. When N[3:0] is equal to the base NAK counter NK[3:0] value in the Endpoint Stall Policy register, a zero-length packet or packet less than maxpacketsize will be issued. |
ST |
A value of 1 means: Endpoint is stalled |
NE |
1 = Enable NAK counter 0 = Disable NAK counter |
USB Endpoint Sta ll Po lic y Re g iste r
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