Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space

8         HOST (PCI/USB) PORT

Figure 8-0.

Listing 8-0.

Table 8-0.

O ve rvie w

The ADSP-2192 can interface with a host computer through its USB port or through its PCI port. Both ports provide access to the host computer via the Peripheral Device Control (PDC) bus, which is connected directly to the IDMA ports on each DSP. The USB port connects through the internal USB interface to the PDC bus, and the PCI port connects through the internal PCI interface to the PDC bus. This chapter describes the PCI parallel interface, and then describes the USB serial interface. The type of bus connection is determined by the BUSMODE[1:0] pins.

Host Port Se le c tion

Four options, selected by the BUSMODE[1:0] pins, specify bus connection to the host. The DSP can detect the BUSMODE configuration and hence the system type by reading bits in the SCFG register (IO space address 0x000).

Table 8-1. BUSMODE Configuration

Mod e Stra p Pin C onne c tions

The BUSMODE[1:0] pin status is sampled at Power-On-Reset. These pins should either be left open or tied directly to GND; no external resistors are necessary. The BUSMODE input pins have a weak internal pull-up resistor (to 2.5V Internal VDD), which is activated only during power-on. After power-on, their state is latched, and then the input receiver and its pull-up resistor are disabled. No DC current flows. Even if the pin voltage floats to a mid-state level, no current is dissipated in the input receiver.

PC I Pa ra lle l Inte rfa c e

The ADSP-2192 includes a 33-MHz, 32-bit PCI interface to provide control and data paths between the device and a host CPU. The PCI interface complies with the PCI Local Bus Specification, Revision 2.2. The interface supports bus mastering as well as bus target interfaces. PCI Bus Power Management Interface Specification, Revision 1.1 is supported, and additional features needed by mini-PCI designs are included.

C onfig ura tion Sp a c e s

The ADSP-2192 has three separate configuration spaces that can be defined to support user functions by writing to the class code register for that function during bootup. Additionally, during boot time, the DSP can disable one or more of the functions. If only two functions are enabled, they will be functions zero and one. If only one function is enabled, it will be function 0.

Each function contains a complete set of registers in the predefined header region, as defined in PCI Local Bus Specification, Revision 2.2. In addition, each function contains optional registers to support PCI Bus Power Management. Registers that are unimplemented or read-only in one function are similarly defined in the other functions. Table 8-2 describes a typical configuration space. 

Table 8-2. PCI Configuration Space

Table 8-2. PCI Configuration Space (Continued)