Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 32

All descriptors can be changed when downloading the RAM based MCU re-numeration code; however the above mentioned restrictions hold for the CONFIG DEVICE.

ADSP-2192 USB Data Pipe Operations

All data transactions involving the generic Endpoints[4:11] stream data into and out of the DSP memory via a dedicated USB hardware block. This hardware block manages all the USB DMA transactions with the DSP memory FIFOs for these Endpoints. While there is no MCU involvement in the management of the data flow through these data pipes, it is the job of the MCU firmware to program the characteristics of these Endpoints via the Endpoint Description, NAK Counter, and Stall Policy registers (MCU Addresses 0x1000-0x1021). Figure 8-27 on page 8-88 is a diagram showing the overall architecture.

USB Bus

Figure 8-27. USB Data Pipe Architecture

The USB data FIFOs for these generic Endpoints exist in DSP memory space. For each Endpoint, there exists the following memory buffer registers (IO Page 0x0C):

As part of initialization, the DSP code is responsible for setting up these FIFOs before USB data transactions for these Endpoints can begin. As noted in the ADSP-2192 product definition, DSP memory addresses cannot exceed 18 bits (0x000000 - 0x03FFFF). When setting up these USB FIFOs, Base + Size/Read Offset/Write Offset cannot be greater than 18 bits.

The DSP memory interface on the ADSP-2192 only allows reads/writes of 16 bit words. It cannot handle byte transactions. Therefore, a 64 byte maxpacketsize means 32 DSP words. A single byte cannot be transferred to/from the DSP. Endpoint 0 does not have this limitation.

Since these FIFOs exist in DSP memory, the DSP is responsible for sharing some of the pointer management duties with the USB core. For OUT transactions, the write pointer is controlled by the USB core and the read pointer is governed by the DSP. The opposite is true for IN transactions. Both the write and read pointers for each memory buffer would start off as 0.

All USB buffers operate in a circular fashion. Once a pointer reaches the end of the buffer, it needs to be set back to zero. The USB core handles this automatically. You can use the DSP DAGS to control auto incrementing and wrapping of the pointers or you can write code to manipulate them manually.

Below is a listing of Read/Write Pointer characteristics:

1.  Both pointers reflect the value of the last memory location on which action took place. The write offset pointer contains the value of the last location written while the read offset pointer contains the value of the last location read.

2.  The USB core pre-increments the pointers before using their value. The DSP code that governs pointer control should follow the same model.

3.  The USB core recognizes when a memory buffer FIFO is empty when the Read pointer = Write pointer. This has certain ramifications, depending upon whether the USB core is handling an OUT transaction or an IN transaction. This is explained in more detail in the following sections concerning USB traffic direction. The USB core recognizes when a memory buffer FIFO is full when the Write pointer is 1 location behind the Read pointer. The DSP code that governs pointer control needs to mimic this behavior.

4.  IO accesses to registers cause DMA transfers to stall for the duration of the IO access. To minimize USB data traffic disturbances, avoid DSP code that programs back-to-back IO accesses. The DSP code that manages the read and write pointer updates must do so via IO access instructions. When writing this code, simply avoid back-to-back IO instructions.