Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 16

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Figure 8-8. USB Endpoint 3 Code Download Base Address Register

The USB Endpoint 3 Code Download Base Address Register contains an 18-bit address that corresponds to the starting location for DSP code download on Endpoint 3. This register is read/write by the MCU only. The most significant bit (DS bit) selects either DSP1 PM address space (DS=0) or DSP2 PM address space (DS=1).

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Figure 8-9. USB Endpoint 1 Code Download Current Write Pointer

Offset Register

The USB Endpoint 1 Code Download Current Write Pointer Offset Register contains an 18-bit address that corresponds to the current write pointer offset from the base address register for DSP code download on Endpoint 1. The sum of this register and the EP1 code download base address register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (-1) when the Endpoint 1 Code Download Base Address Register is updated.

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Figure 8-10. USB Endpoint 2 Code Download Current Write Pointer Offset Register

The USB Endpoint 2 Code Download Current Write Pointer Offset Register contains an 18-bit address that corresponds to the current write pointer offset from the base address register for DSP code download on Endpoint 2. The sum of this register and the EP2 code download base address register represents the last DSP PM location written.