Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 6

Each DSP IO space transaction is translated into a PDC bus transaction in hardware. The initiating DSP waits for its IO Acknowledge (IOACK) signal until the transaction is granted and completed. While waiting, DSP execution is halted at the IO space access instruction, and the DSP cannot complete any other task. In this state, interrupts are ignored, DMA cannot take place, and no other instruction may execute.

Example

DSP#2 is in the middle of a PDC bus transaction, and every initiator wants to launch a PDC bus transaction. DSP #2 cannot start a new transaction until the current IO space access instruction completes. DSP #1 halts, waiting for IOACK, until its transaction is granted and completed. DSP #1 may attempt to lock the bus and check for bus lock status. If the bus was not locked by DSP #1, it assumes that a transaction is in progress and may remove the lock request and try again later.

The PCI bus cannot initiate a transaction and is issued a Retry semantic.

The USB bus cannot initiate a transaction and is issued a Retry semantic. The sub-ISA bus cannot initiate a transaction and does not receive an ISA acknowledge until the transaction is granted and completed.

A zero wait state PDC transaction consumes approximately 12 DSP cycles. Most transactions have zero wait states, but some transactions (those that must be mapped through external interfaces, for example) may be much longer.

Resets

In addition to power-on and system resets described in other chapters, the ADSP-2192 can be reset by the PCI or USB bus. The Reset Handler that gets executed is dictated by the CRST[1:0] bits in the Chip Mode/Status Register (CMSR). For PCI or USB Reset, set the CRST bits to [1:0].

Inte rrup ts

Table 8-5 on page 8-15 shows a variety of potential sources of interrupts to the PCI host. The PCI Interrupt Register consolidates all of the possible interrupt sources and the bits of this register to a single interrupt pin, INTA#, used to signal the interrupts back to the host. The register bits are set by the various sources and can be cleared by writing a 1 to the bits to be cleared.

Interrupts may be sensitive either to edges or levels, as indicated in

Table 8-5 on page 8-15. The PCI GPIO interrupt is level sensitive, and is asserted when any of the GPIO’s individual sticky status bits is true. If an interrupt service routine is in the process of acknowledging one GPIO interrupt (by clearing its sticky status and then writing a 1 to PCIINT:GPIO) while an event occurs on another GPIO, it is possible for the ISR to miss the second event, should it occur between the time the ISR reads the GPIO’s status and when the ISR clears the PCIINT:GPIO bit.

The GPIO interrupt is level sensitive to accommodate this case; the PCIINT:GPIO interrupt bit and the INTA# pin immediately reassert after clearing. The ISR may be written in two ways to detect this case: it may exit and be immediately retriggered, or it may read back the PCIINT register after the clear to see if any bit has been set again, which indicates the occurrence of some new interrupt. Table 8-5. PCI Interrupt Registe r