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Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 9

Bit	Type	Description
10	R/WC	OutBox0 DSP 2 Interrupt Pending. This bit is set when the PCI acknowledges reading data from OutBox0 by writing a 1 to bit 14, if enabled by the corresponding Mailbox Control Reg bit.
11	R/WC	OutBox1 DSP 2 Interrupt Pending. This bit is set when the PCI acknowledges reading data from OutBox1 by writing a 1 to bit 15, if enabled by the corresponding Mailbox Control Reg bit.

C ontrol

This register consists of read/write interrupt enable control bits (denoted R/W). See “ADSP-2192 DSP Peripheral Registers” on page B-1 for the bit names of the MBXCTL register.

Table 8-8. Mailbox Control Register

Bit	Type	Description
0	R/W	InBox0 PCI Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
1	R/W	InBox1 PCI Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
2	R/W	OutBox0 PCI Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
3	R/W	OutBox1 PCI Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
4	R/W	InBox0 DSP #1 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.

Table 8-8. Mailbox Control Register (Continued)

Bit	Type	Description
5	R/W	InBox1 DSP #1 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
6	R/W	OutBox0 DSP #1 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
7	R/W	OutBox1 DSP #1 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
8	R/W	InBox0 DSP #2 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
9	R/W	InBox1 DSP #2 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
10	R/W	OutBox0 DSP #2 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
11	R/W	OutBox1 DSP #2 Interrupt Enable. When asserted allows the corresponding Interrupt Pending bit to be set.
15:12	RO	Reserved

Ind ire c t A c c e ss to I/O Sp a c e

PCI I/O access to the ADSP-2192 registers is supported via BAR4. The registers listed in Table 8-9 are directly accessible from BAR4.

Table 8-9. I/O Space Indirect Access Registers

Offset	Name	Reset	Comments
0x03-0x00	IOREGA Control Register Address	0x0000	Address and direction control for registers access
0x07-0x04	IOREGD Control Register Data	0x0000	Data for register access
0x0B-0x08	IOMEMA DSP Memory Addresses	0x00000000	Address and direction control for DSP memory access
0x0F-0x0C	IOMEMD DSP Memory Data	0x000000	Data for DSP memory access

To access the PCI I/O space registers:

1. Write IOREGA with the register address, setting bit 14 for direction control. If the access is a read, the register is prefetched into the IOREGD register.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

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