|
Address |
Name |
Comments |
|
Command Register Bit 2 |
Bus Master Enable |
Enables are separate in each function, go along with the function’s base addresses |
|
Command Register Bit 3 |
Special Cycles |
None of the functions support special cycles, read-only |
|
Command Register Bit 4 |
Memory Write and Invalidate |
No function generates Memory Write and Invalidate commands, read-only |
|
Command Register Bit 5 |
VGA Palette Snoop |
Not applicable, read-only |
|
Command Register Bit 6 |
Parity Error Response |
If any function has the bit set, PERR# may be asserted |
|
Command Register Bit 7 |
Stepping Control |
No address stepping is done, read-only |
|
Command Register Bit 8 |
SERR# Enable |
If any function enables SERR# driver, then SERR# may be asserted |
|
Command Register Bit 0 |
Fast Back-to-back Enable |
No function generates fast back-to-back transactions |
|
Status Register Bit 4 |
Capabilities List |
Read-only. |
|
Status Register Bit 5 |
66 Mhz Capable |
Read-only. |
|
Status Register Bit 6 |
Reserved |
Read-only. |
|
Status Register Bit 7 |
Fast Back-to-back Capable |
Read-only. |
|
Status Register Bit 8 |
Master Data Parity Error |
Separate for each function, no interaction |
Table 8-3. Configuration Space—Function Interactions (Continued)
|
Address |
Name |
Comments |
|
Status Register Bit 10:9 |
DEVSEL Timing |
Read-only. |
|
Status Register Bit 11 |
Signaled Target Abort |
Separate for each function, no interaction |
|
Status Register Bit 12 |
Received Target Abort |
Separate for each function, no interaction |
|
Status Register Bit 13 |
Received Master Abort |
Separate for each function, no interaction |
|
Status Register Bit 14 |
Signaled System Error |
Separate for each function, set if SERR# enabled and SERR# asserted |
|
Status Register Bit 15 |
Detected Parity Error |
Separate for each function, but set in all functions simultaneously |
|
Revision ID |
Read-only. |
|
|
Class Code |
Separate registers, no interaction |
|
|
Cache Line Size |
Read-only. |
|
|
Latency Timer |
Separate for each function, no interaction |
|
|
Header Type |
Read-only. |
|
|
Base Address 1 |
In range signal ORed between functions, any function can access memory |
|
|
Base Address 2 |
In range signal ORed between functions, any function can access memory |
|
|
Base Address 3 |
In range signal ORed between functions, any function can access memory |
Table 8-3. Configuration Space—Function Interactions (Continued)
|
Address |
Name |
Comments |
|
Base Address 4 |
In range signal ORed between functions, any function can access memory |
|
|
Subsystem Vendor ID |
Separate registers, no interaction |
|
|
Subsystem Device ID |
Separate registers, no interaction |
|
|
Capabilities Pointer |
Read-only. |
|
|
Interrupt Line |
Separate registers, no interaction |
|
|
Interrupt Pin |
Read-only. |
|
|
Min_Gnt |
Read-only. |
|
|
Max_Lat |
Read-only. |
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