Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 17

This register is read by the MCU only and is cleared to 3FFFF (-1) when the Endpoint 2 Code Download Base Address Register is updated.

Figure 8-11. USB Endpoint 3 Code Download Current Write Pointer Offset Register

The USB Endpoint 3 Code Download Current Write Pointer Offset Register contains an 18-bit address that corresponds to the current write pointer offset from the base address register for DSP code download on Endpoint 3. The sum of this register and the EP3 code download base address register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (-1) when the Endpoint 3 Code Download Base Address Register is updated.

The USB SETUP Token Command Register is defined as 8 bytes long and contains the data sent on the USB from the most recent SETUP transaction. This register is read by the MCU only.

Table 8-15. USB SETUP Token Command Register

Byte        7                                             0

0

1

2

3

4

5

6

7

If the most recent SETUP transaction involves a data OUT stage, the USB SETUP Token Data Register is defined as 8 bytes long and contains the data sent on the USB during the data stage. This is also where the MCU writes data to be sent in response to a SETUP transaction involving a data IN stage. This register is read/write by the MCU only.

Table 8-16. USB SETUP Token Data Register

Byte        7                                             0

0

1

2

3

4

5

6

7

Figure 8-12. USB SETUP Counter Register

The USB SETUP Counter Register provides information about the total size of the SETUP transaction data stage. This register is read/write by the

MCU only.

C[3:0]       Counter bits.

The counter hardware is a modulo 4-bit down counter used for tallying data bytes in both the IN and OUT data stages of SETUP transactions. As such, the count value stored has different meanings.