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Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 7

Table 8-5. PCI Interrupt Register (Continued)

Bit

Name

Comments1

Sensitivity

4

Tx1 DMA Channel Interrupt

Transmit Channel 1 Bus Master Transactions

Edge

3

Tx0 DMA Channel Interrupt

Transmit Channel 0 Bus Master Transactions

Edge

2

Rx1 DMA Channel Interrupt

Receive Channel 1 Bus Master Transactions

Edge

1

Rx0 DMA Channel Interrupt

Receive Channel 0 Bus Master Transactions

Edge

0

Reserved

1  The Interrupt Status is Latched even when the Interrupt Source is not enabled. Therefore, the Interrupt should be cleared before being enabled unless previous Interrupt history is considered important.

PCI Control Register

The PCI Control Register must be initialized by the DSP ROM code prior to PCI enumeration. (It has no effect in ISA or USB mode.) Once the Configuration Ready bit is set to 1, Bits[2:0] of the PCI Control Register become read-only, and further write access by the DSP to configuration space is disallowed.  Table 8-6. PCI Control Register

Bit

Name

Comments

15

Reserved

14

TAbort IEN

PCI Target Abort Interrupt Enable.

PCI Interface Target Abort Detect Int. Enabled.

Table 8-6. PCI Control Register (Continued)

Bit

Name

Comments

13

MAbort IEN

PCI Master Abort Interrupt Enable.

PCI Interface Master Abort Detect Int. Enabled.

12

AC’97 IEN

AC’97 Interrupt Enable.

AC’97 Interface Initiated Interrupt Enabled.

11

GPIO IEN

GPIO Interrupt Enable.

I/O Pin Initiated Interrupt Enabled.

10

Reserved

9

Reserved

8

D2PM1 IEN

Mailbox 1 PCI Interrupt Enable.

DSP to PCI Mailbox 1

Transfer Interrupt Enabled.

7

D2PM0 IEN

Mailbox 0 PCI Interrupt Enable.

DSP to PCI Mailbox 0

Transfer Interrupt Enabled.

6

P2DM1 IEN

Mailbox 1 PCI Interrupt Enable.

PCI to DSP Mailbox 1

Transfer Interrupt Enabled.

5

P2DM0 IEN

Mailbox 0 PCI Interrupt Enable.

PCI to DSP Mailbox 0

Transfer Interrupt Enabled.

4

Reserved

3

Reserved

2

Conf Rdy

Configuration Ready

When 0, disables PCI accesses to the ADSP-2192 (terminated with Retry). Must be set to 1 by DSP ROM code after initializing configuration space. Once 1, cannot be written to 0.

1-0

PCIF[1:0]

Number of PCI Functions Configured

00 = one PCI Function enabled, 01= two functions, 10= three functions

PC I Port Priority on the PDC Bus

The PCI port shares use of the Peripheral Device Control (PDC) bus with the two DSPs and with other I/O ports. Transactions may be initiated by either DSP or by the external bus interface (whether PCI, USB, or Sub-ISA). Transactions may be targeted at registers for PCI, USB, system control, or serial port functions. Only one transaction may be in progress at a time; all other initiators must wait for the current transaction to complete.

The prioritization between the different possible masters is fixed. The priorities from highest to lowest are: DSP #1, DSP #2, Host (PCI/USB) interface.

The syntax for access to the PDC registers is described in “ADSP-2192 DSP Peripheral Registers” on page B-1.

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