Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 37

/**********************************************************/

#define   PCI_MSTRCNT0       0x880      /*  DMA Transfer Count0 Bus master sample */

/*  transfer count 0 */ #define   PCI_MSTRCNT1       0x882     /*  DMA Transfer Count1 Bus master sample */

/*  transfer count 1 */

#define   PCI_DMAC0          0x884/*  DMA Control0 Bus master control and status 0 */

#define   PCI_DMAC1          0x886/*  DMA Control1 Bus master control and status 1 */

#define   PCI_IRQSTAT        0x888 /*  PCI Interrupt Reg Status bits for all PCI */

/* interrupt sources */

#define   PCI_CFGCTL         0x88A /*  PCI Control Includes config register */ /* read/write control */

/***************** PCI_DMAC0-1 Bit definitions ************/

#define DEN    0   /* DMA Enable */

#define TRAN   1   /* DMA Direction */

#define FLSH   2   /* Flush FIFO */

#define DSP    3   /* DSP P0/P1 Select */

#define DPD    4   /* DMA Packing Disable, Double Word Mode */

#define CFG2   7   /* Configuration Select 2, 1, or 0 */

#define CFG1   6   /* Configuration Select 2, 1, or 0 */

#define CFG0   5   /* Configuration Select 2, 1, or 0 */ #define EMPTY  8   /* DMA FIFO Empty Status */

#define HALT   9   /* DMA Channel Halt Status */

#define LOOP  10   /* DMA Channel Loop Status */

/**********************************************************/

#endif

The following example definitions file is for the ADSP-2192 DSP USB. For the most current definitions file, programs should use the version of this file that comes with the software development tools. The version of the file that appears here is included as a guide only.

/* ----------------------------------------------------------------------------def2192_USB.h - SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-2192 Created November 21, 2000. Copyright Analog Devices, Inc.

Note:   This file is based on preliminary technical data and is subject to change. Updates will be posted on the Analog Devices FTP site:

ftp.analog.com

-----------------------------------------------------------------------------*/ #ifndef __DEF2192_USB_H_

#define __DEF2192_USB_H_

/*Chip Control Registers (DSP IOPAGE=0x00)*/

#define   SYSCON    0x00   /*  Chip Mode/Status Register       */ #define   PWRCFG0   0x02   /*  Function 0 Power Management     */

#define   PWRCFG1   0x04   /*  Function 1Power Management      */

#define   PWRCFG2   0x06   /*  Function 2 Power Management     */ #define   PWRP0     0x08   /*  DSP 0 Interrupt/Power down      */ #define   PWRP1     0x0A   /*  DSP 1 Interrupt/Power down      */ #define   PLLCTL    0x0C   /*  DSP PLL Control                 */

#define   REVID     0x0E   /*  ADSP-2192 Revision ID (read only)  */

/*GPIO Control Registers (DSP IOPAGE=0x00)*/

#define   GPIOCFG      0x10 /*  GPIO Config Direction Control (1 = in, 0 = out) */

#define   GPIOPOL      0x12 /*  GPIO Polarity Inputs: 0 = active hi,            */

/*  1 = active lo; Outputs: 0 = CMOS, 1 = Open Drain*/ #define   GPIOSTKY     0x14 /*  GPIO Sticky: 1 = sticky, 0 = not sticky         */

#define   GPIOWAKECTL  0x16 /*  GPIO Wake Control: 1 = wake-up enabled          */

/*  (requires sticky set)                           */

#define   GPIOSTAT     0x18 /*  GPIO Status (Read = Pin state;                  */

/*  Write: 0 = clear sticky status, 1 = no effect)  */

#define   GPIOCTL      0x1A /*  GPIO Control(w), Init(r) (Read = Power-on state; */

/*  Write : Set state of output pins)               */

#define   GPIOPUP      0x1C /*  GPIO Pull-up Pull-up enable                     */

/*  (if input): 1 = enable, 0 = hi-Z                */

#define   GPIOPDN      0x1E /*  GPIO Pull-down Pull-down enable                 */ /*  (if input): 1 = enable, 0 = hiZ                 */

/*PCI/USB Mailbox Registers (DSP IOPAGE=0x00)*/