Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 4

Ba se A d d re ss Re g iste rs

Each function contains four base address registers used to access

ADSP-2192 control registers and DSP memory. Base Address Register 1 (BAR1) points to the control registers; the address specified for each of the functions is an offset from BAR1. PCI memory-type accesses read and write the registers. Byte-wide accesses to the control registers are supported only for those registers within the PCI interface itself.

DSP memory accesses use BAR2 or BAR3 of each function. BAR2 is used to access 24-bit DSP memory, and BAR3 accesses 16-bit DSP memory. The lower half of the allocated space pointed to by each DSP memory BAR is the DSP memory for DSP #1. The upper half is the memory space associated with DSP #2. PCI transactions to and from DSP memory use the DMA function within the DSP core. Each word transferred to or from PCI space uses a single DSP clock cycle to perform internal DSP data transfer. Byte-wide accesses to DSP memory are not supported.

I/O type accesses are supported via BAR4. Both the control registers accessible via BAR1 and the DSP memory accessible via BAR2 and BAR3 can be accessed with I/O accesses. Indirect access is used to read and write the control registers and the DSP memory. For control register accesses, an address register points to the word to be accessed and a separate register is used to transfer the data. Read/write control is part of the address register. Only 16-bit accesses are possible via the I/O space. A separate set of registers performs the same function for DSP memory access. Control for these accesses includes a 24-bit/16-bit select as well as direction control. The data register for DSP memory access is 24-bits wide. 16-bit accesses are loaded into the lower 16 bits of the register.

Pe rip he ra l De vic e C ontrol Re g iste rs

The Peripheral Device Control Register space is distributed throughout the ADSP-2192 and connected through the Peripheral Device Control Bus. The PCI bus can access the Peripheral Device Control Registers directly. PCI Base Address Register 1 (BAR1) points to the Control Registers (including the Peripheral Device Control Registers). PCI register accesses are byte wide. PCI register addresses are 24 bits long. Registers can be accessed only in PCI Bus Target/Slave mode.

Powe r Ma na g e m e nt Inte ra c tions

Conflicts can occur with three functions. Table 8-4 on page 8-10 identifies these potential conflicts and provides suggested resolutions.

Target accesses to registers and DSP memory can go through any function. If the Memory Space access enable bit is set in that function, PCI memory accesses (whose address matches the locations programmed into functions BAR[3:1]) can read or write any visible register or memory location within the ADSP-2192. Similarly, if I/O Space access enable is set, PCI I/O accesses can be performed via BAR4.

There are interactions within the Power Management section of the configuration blocks. The device stays in the highest power state of the three functions. When one of the functions is in a low power state, it can respond only to configuration accesses, regardless of the power state of the other functions. Similarly, when a function transitions from power management state D3 to D0 (see Chapter 11 “System Design”), that function’s configuration space is reinitialized. Each function has a separate PME enable bit and PME status bit. When no determination is possible, both PME status bits are set.

Table 8-4. Power Management—Function Interactions