Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 10

2.  Read the IOREGD register for the appropriate data. The Ready status is not necessary in PCI mode, since the IOREGD access is retried until the data is ready.

3.  For writes, the register transaction is initiated when the IOREGD register is written.

To access PCI Memory:

1.  Write IOMEMA with the DSP Memory address, setting the read/write control and the 16/24-bit control appropriately.

2.  The data is prefetched for reads. The address automatically increments for memory accesses, allowing subsequent IOMEMD reads from the subsequent locations.

3.  Consecutive writes to IOMEMD are written to consecutive memory locations.

Table 8-10. BIT Organization of PCI I/O Space Registers

USB Inte rfa c e

O ve rvie w

The USB port on the ADSP-2192 complies with the Universal Bus Specification, Version 1.1 and allows you to interface with a compatible host. An 8051 compatible MCU is supported on board, which allows you to soft download different configurations and support any number of class specific commands.

In addition to the 8051 core, the interface includes USB accessible registers, an interrupt subsystem, configuration and clock control, and a data path that allows USB Endpoint data transfer directly between the DSP internal memory and a USB-host. The module interfaces with an on-chip USB transceiver on the USB side and the DMA and PDC bus on the ADSP-2192 system side.

USB Requirements

This section describes some features of the protocol upon which this USB implementation has been based. A separate reference section lists the resources that provide the detailed description of the USB.

USB is a master-slave bus, in which a single master generates data transfer requests to the attached slaves and allocates bandwidth on the serial cable according to a specific algorithm. The bus master is referred to as the USB host, and the bus slaves are referred to as USB devices. Each USB device implements one or more USB Endpoints which are akin to virtual data channels. Each Endpoint on a USB device operates independently of all others.

Data flows between the USB Host and attached devices in packets that are 8, 16, 32, or 64 bytes. The packets are grouped into larger units called transfers.

The USB Host implements a traffic scheduling algorithm to allocate the serial bus bandwidth fairly across all of the attached USB devices and Endpoints. From the point of view of a USB device, this algorithm is not deterministic. While the specific scheduling algorithm is standardized, the bus dynamically reallocates bandwidth based on criteria such as packet error conditions and flow control. As far as the device is concerned, it can transfer requests for any Endpoint at any time. Depending upon the bus loading at any given time, the USB Host may request packets back-to-back, or it may request packet transfers to each Endpoint in a round-robin fashion. The USB protocol also allows for detection and retransmission of packets in cases of bit errors and flow-control.

Any USB device implementation must maintain state information for each of its Endpoints which allow large data transfers to occur one packet at a time and each packet to be retransmitted, if necessary.

Im p le m e nta tion

The USB module in ADSP-2192 has the following features:

•  Control Endpoint for all USB control transactions including downloading application-specific MCU firmware