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Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 8

DSP Ma ilb ox Re g iste rs

The DSP Mailbox registers allow you to construct an efficient communications protocol between the PCI device driver and the DSP code. The mailbox functions consist of InBox0, InBox1, OutBox0, OutBox1, a status register, and a control register.

InBox e s

The incoming mailboxes (InBox0 and InBox1) are 16 bits wide. They may be read or written by the PCI device or the DSP core. PCI writes to the InBoxes may generate DSP interrupts. DSP reads of InBoxes may generate PCI interrupts.

O utBox e s

The outgoing mailboxes (OutBox0 and OutBox1) are 16 bits wide. They may be read or written by the PCI device or the DSP core. DSP writes to the OutBoxes may generate PCI interrupts.

PCI reads of OutBoxes may generate DSP interrupts with special handling. The PC host must perform the following sequence when reading an outbox:

1. Read OutBox

2. Write a 1 to the OutBox Valid bit to clear it

PCI reads of OutBoxes cannot generate interrupts directly, as they would be “read side-effects” which are prohibited in the PCI Specification.

Sta tus

This register consists of read/write-one-clear status bits (denoted R/WC). A read/write-one-clear bit is cleared when a one is written to it. Writing a zero has no effect. See “ADSP-2192 DSP Peripheral Registers” on page B-1 for the bit names of the MBXSTAT register.

Table 8-7. Mailbox Status Register

Bit	Type	Description
0	R/WC	InBox0 PCI Interrupt Pending. This bit is set when the DSP reads valid data from InBox0, if enabled by the corresponding Mailbox Control Register bit.
1	R/WC	InBox1 PCI Interrupt Pending. This bit is set when the DSP reads valid data from InBox1, if enabled by the corresponding Mailbox Control Register bit.

Table 8-7. Mailbox Status Register (Continued)

Bit	Type	Description
2	R/WC	OutBox0 PCI Interrupt Pending. This bit is set when the DSP writes valid data to OutBox0, if enabled by the corresponding Mailbox Control Register bit.
3	R/WC	OutBox1 PCI Interrupt Pending. This bit is set when the DSP writes valid data to OutBox1, if enabled by the corresponding Mailbox Control Register bit.
4	R/WC	InBox0 DSP 1 Interrupt Pending. This bit is set when the PCI writes valid data to InBox0, if enabled by the corresponding Mailbox Control Register bit.
5	R/WC	InBox1 DSP 1 Interrupt Pending. This bit is set when the PCI writes valid data to InBox1, if enabled by the corresponding Mailbox Control Register bit.
6	R/WC	OutBox0 DSP 1 Interrupt Pending. This bit is set when the PCI acknowledges reading data from OutBox0 by writing a 1 to bit 14, if enabled by the corresponding Mailbox Control Reg bit.
7	R/WC	OutBox1 DSP 1 Interrupt Pending. This bit is set when the PCI acknowledges reading data from OutBox1 by writing a 1 to bit 15, if enabled by the corresponding Mailbox Control Reg bit.
8	R/WC	InBox0 DSP 2 Interrupt Pending. This bit is set when the PCI writes valid data to InBox0, if enabled by the corresponding Mailbox Control Register bit.
9	R/WC	InBox1 DSP 2 Interrupt Pending. This bit is set when the PCI writes valid data to InBox1, if enabled by the corresponding Mailbox Control Register bit.

Table 8-7. Mailbox Status Register (Continued)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

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