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Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 22

Address <15:15> = 1 indicates a read from the MCU register space, and Address <15:15> = 0 indicates a read from the DSP register space. When accessing DSP register space, the MCU must write the address to be read to the USB Register I/O Address register. Bit 15 of the USB Register I/O Address register starts the transaction and bit 14 is set to zero to indicate a READ. The data read is placed into the USB Register I/O Data register. The MCU polls Bit 15 of the USB Register I/O Address Register, looking for a value of 0, which indicates that the read cycle has completed.

USB REGIO (register read) is a three-stage control transfer with an IN data stage. Stage 1 is the SETUP stage, stage 2 is the data stage involving the IN packet, and stage 3 is the status stage.

DSP Re g iste r De finitions

For each Data Endpoint, four registers provide a memory buffer in the DSP DM (Data Memory) space. These registers are defined for each Endpoint shared by all interfaces for a total of 4x8 = 32 registers. These registers are read/write by the DSP. The USB Data Pipe hardware block also has access to them as part of its buffer management duties.

USB DSP Re g iste r De finitions

Table 8-30. USB DSP Register Definitions

Page	Address	Name
0x0C	0x00-0x03	DSP Memory Buffer Base Addr EP4
0x0C	0x04-0x05	DSP Memory Buffer Size EP4
0x0C	0x06-0x07	DSP Memory Buffer RD Offset EP4
0x0C	0x08-0x09	DSP Memory Buffer WR Offset EP4
0x0C	0x10-0x13	DSP Memory Buffer Base Addr EP5
0x0C	0x14-0x15	DSP Memory Buffer Size EP5
0x0C	0x16-0x17	DSP Memory Buffer RD Offset EP5
0x0C	0x18-0x19	DSP Memory Buffer WR Offset EP5
0x0C	0x20-0x23	DSP Memory Buffer Base Addr EP6
0x0C	0x24-0x25	DSP Memory Buffer Size EP6
0x0C	0x26-0x27	DSP Memory Buffer RD Offset EP6
0x0C	0x28-0x29	DSP Memory Buffer WR Offset EP6

Table 8-30. USB DSP Register Definitions (Continued)

Page	Address	Name
0x0C	0x30-0x33	DSP Memory Buffer Base Addr EP7
0x0C	0x34-0x35	DSP Memory Buffer Size EP7
0x0C	0x36-0x37	DSP Memory Buffer RD Offset EP7
0x0C	0x38-0x39	DSP Memory Buffer WR Offset EP7
0x0C	0x40-0x43	DSP Memory Buffer Base Addr EP8
0x0C	0x44-0x45	DSP Memory Buffer Size EP8
0x0C	0x46-0x47	DSP Memory Buffer RD Offset EP8
0x0C	0x48-0x49	DSP Memory Buffer WR Offset EP8
0x0C	0x50-0x53	DSP Memory Buffer Base Addr EP9
0x0C	0x54-0x55	DSP Memory Buffer Size EP9
0x0C	0x56-0x57	DSP Memory Buffer RD Offset EP9
0x0C	0x58-0x59	DSP Memory Buffer WR Offset EP9
0x0C	0x60-0x63	DSP Memory Buffer Base Addr EP10
0x0C	0x64-0x65	DSP Memory Buffer Size EP10
0x0C	0x66-0x67	DSP Memory Buffer RD Offset EP10
0x0C	0x68-0x69	DSP Memory Buffer WR Offset EP10
0x0C	0x70-0x73	DSP Memory Buffer Base Addr EP11
0x0C	0x74-0x75	DSP Memory Buffer Size EP11
0x0C	0x76-0x77	DSP Memory Buffer RD Offset EP11

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