Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 18

                       c_in_i <= '1';

                     end if;

                     if s_valid_i_1 = '1' then

                       if c_out_i_1 = '0' then

                         m_buf <= s_i_1;

                       else

                         m_buf <= s_i_2;

                       end if;

                     end if;

 

        when shift => a_exp <= a_exp(1022 downto 0) & '0';

        when mod2 => if add_ready_1 = '1' and add_ready_2 = '1' then

                       add_start_1 <= '1';

                       add_start_2 <= '1';

                       add_i <= '1';

                       a_i <= a_exp;

                       b_i_1 <= n_buf_not_1;

                       b_i_2 <= n_buf_not_2;

                       c_in_i <= '1';

                     end if;

                     if s_valid_i_1 = '1' then

                       if c_out_i_1 = '0' then

                         a_exp <= s_i_1;

                       else

                         a_exp <= s_i_2;

                       end if;

                     end if; 

        when inc_j => j <= j + 1;

                      b_buf_tmp <= '0' & b_buf_tmp(1023 downto 1);

        when output => if add_ready_1 = '1' then

                         add_start_1 <= '1';

                         add_i <= '1';

                         a_i <= m_buf;

                         b_i_1 <= n_buf_not_1;

                         c_in_i <= '1';

                       end if;

                       if s_valid_i_1 = '1' then

                         m_valid <= '1';

                         m <= m_buf;

                         if c_out_i_1 = '1' then

                           m <= s_i_1;

                         end if;

                       end if;

        when others => null;

      end case;

    end if;

  end if;

end process;

end architecture;

Текст файла « mult_1024.vhd» :

-- 1024-bit Multiplication

-- m = a*b

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity mult_1024 is

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        M_valid : out std_logic;

        M: OUT std_logic_VECTOR(1023 downto 0));

end mult_1024;

architecture my_mult of mult_1024 is

component add_sub_1024

        port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        C_IN: IN std_logic;

        C_OUT: OUT std_logic;

        ADD: IN std_logic;

        s_valid : out std_logic;

        S: OUT std_logic_VECTOR(1023 downto 0));

end component;

signal a_i,b_i,s_i: std_logic_vector(1023 downto 0);

signal add_ready, add_start : std_logic;

signal s_valid_i : std_logic;

signal add_i : std_logic;

signal c_in_i : std_logic;

signal c_out_buf : std_logic;

signal b_buf_tmp : std_logic_vector(1023 downto 0);

signal k,j : integer;

signal a_buf, a_exp, b_buf, m_buf : std_logic_vector(1023 downto 0);

signal reset_l_1 : std_logic;

type add_state is (idle, cal_k, add1, shift, inc_j, output);

signal state, nxstate : add_state;

begin

my_add_sub : add_sub_1024

   port map (

             clk => clk,

             reset_l => reset_l_1,

             start => add_start,

             ready => add_ready,

             A => a_i,

             B => b_i,

             C_IN => c_in_i,

             C_OUT => open,

             ADD => add_i,

             s_valid => s_valid_i,

             S => s_i);

process(clk)

begin

  if clk'event and clk = '1' then

    reset_l_1 <= reset_l;

  end if;

end process;

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      state <= idle;

    else

      state <= nxstate;

    end if;

  end if;

end process;