Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 17

                 end if;

    when mod1 => if s_valid_i_1 = '1' then

                   nxstate <= shift;

                 end if;

    when shift => if a_exp(1023) = '1' then

                    nxstate <= mod2;

                  else

                    nxstate <= inc_j;

                  end if;

    when mod2 => if s_valid_i_1 = '1' then

                   nxstate <= inc_j;

                 end if;

    when inc_j => if j = k then

                    nxstate <= output;

                  elsif b_buf_tmp(0) = '0' then

                    nxstate <= shift;

                  else

                    nxstate <= add1;

                  end if;

    when output => if s_valid_i_1 = '1' then

                     nxstate <= idle;

                   end if;

    when others => nxstate <= idle;

  end case;

end process mod_mult_fsm;

process(clk)

variable not_n_v : std_logic_vector(1023 downto 0);

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      m <= (others => '0');

      ready <= '0';

      m_valid <= '0';

      a_i <= (others => '0');

      b_i_1 <= (others => '0');

      b_i_2 <= (others => '0');

      c_in_i <= '0';

      add_i <= '1';

      add_start_1 <= '0';

      add_start_2 <= '0';

      k <= 1024;

      j <= 1;

      b_buf_tmp <= (others => '0');

      a_exp <= (others => '0');

      a_buf <= (others => '0');

      b_buf <= (others => '0');

      m_buf <= (others => '0');

      n_buf_not_1 <= (others => '0');

      n_buf_not_2 <= (others => '0');

      not_n_v := (others => '0');

--      c_out_buf <= '0';

    else

      ready <= '0';

      m_valid <= '0';

      a_i <= (others => '0');

      b_i_1 <= (others => '0');

      b_i_2 <= (others => '0');

      c_in_i <= '0';

      add_start_1 <= '0';

      add_start_2 <= '0';

      case state is

        when idle => k <= 1024;

                     j <= 1;

                     ready <= '1';

                     m <= (others => '0');

                     b_buf_tmp <= (others => '0');

                     a_exp <= (others => '0');

                     a_buf <= (others => '0');

                     b_buf <= (others => '0');

                     m_buf <= (others => '0');

                     n_buf_not_1 <= (others => '0');

                     n_buf_not_2 <= (others => '0');

--                     c_out_buf <= '0';

                     if reset_l_1 = '1' and start = '1' then

                       ready <= '0';

                       a_buf <= a;

                       b_buf <= b;

                       not_n_v := not n;

                       n_buf_not_1 <= not_n_v;

                       n_buf_not_2 <= not_n_v(1022 downto 0) & '1';

                       b_buf_tmp <= b;

                       a_exp <= a;

                     end if;

        when cal_k => if b_buf_tmp(1023) = '0' then

                        k <= k - 1;

                        b_buf_tmp <= b_buf_tmp(1022 downto 0) & '0';

                      else

                        b_buf_tmp <= '0' & b_buf(1023 downto 1);

                      end if;

        when add1 => if add_ready_1 = '1' then

                       add_start_1 <= '1';

                       add_i <= '1';

                       a_i <= a_exp;

                       b_i_1 <= m_buf;

                       c_in_i <= '0';

                     end if;

                     if s_valid_i_1 = '1' then

--                       c_out_buf <= c_out_i_1;

                       m_buf <= s_i_1;

                     end if;

        when mod1 => if add_ready_1 = '1' and add_ready_2 = '1' then

                       add_start_1 <= '1';

                       add_start_2 <= '1';

                       add_i <= '1';

                       a_i <= m_buf;

                       b_i_1 <= n_buf_not_1;

                       b_i_2 <= n_buf_not_2;