Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 15

signal a_buf, b_buf, e_buf, n_buf : std_logic_vector(1023 downto 0);

signal reset_l_1 : std_logic;

type add_state is (idle, cal_k, mult1, mult2, output);

signal state, nxstate : add_state;

begin

my_mod_mult : mod_mult_1024

   port map (

             clk => clk,

             reset_l => reset_l_1,

             start => mult_start,

             ready => mult_ready,

             A => a_i,

             B => b_i,

             N => n_buf,

             M_valid => m_valid_i,

             M => m_i);

process(clk)

begin

  if clk'event and clk = '1' then

    reset_l_1 <= reset_l;

  end if;

end process;

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      state <= idle;

    else

      state <= nxstate;

    end if;

  end if;

end process;

mod_mult_fsm: process(k, state, reset_l_1, start, m_valid_i, b_buf)

begin

  nxstate <= state;

  case state is

    when idle => if reset_l_1 = '1' and start = '1' then

                   nxstate <= cal_k;

                 end if;

    when cal_k => if k /= 0 then

                    if b_buf(1023) = '1' then

                      nxstate <= mult1;

                    end if;

                  else

                    nxstate <= output;

                  end if;

    when mult1 => if m_valid_i = '1'then

                   if k /= 0 then

                     nxstate <= mult2;

                   else

                     nxstate <= output;

                   end if;

                 end if;

    when mult2 => if m_valid_i = '1' then

                   if b_buf(1023) = '1' then

                     nxstate <= mult1;

                   elsif k = 0 then

                     nxstate <= output;

                   end if;

                  end if;

    when output => nxstate <= idle;

    when others => nxstate <= idle;

  end case;

end process mod_mult_fsm;

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      e <= (others => '0');

      ready <= '0';

      e_valid <= '0';

      a_i <= (others => '0');

      b_i <= (others => '0');

--      m_i <= (others => '0');

      k <= 1023;

      a_buf <= (others => '0');

      b_buf <= (others => '0');

      e_buf <= (others => '0');

      n_buf <= (others => '0');

    else

      ready <= '0';

      e_valid <= '0';

      a_i <= (others => '0');

      b_i <= (others => '0');

      mult_start <= '0';

      case state is

        when idle => k <= 1023;

                     ready <= '1';

                     e <= (others => '0');

                     a_buf <= (others => '0');

                     b_buf <= (others => '0');

                     e_buf(1023 downto 1) <= (others => '0');

                     e_buf(0) <= '1';

                     n_buf <= (others => '0');

                     if reset_l_1 = '1' and start = '1' then

                       ready <= '0';

                       a_buf <= a;

                       b_buf <= b;

                       n_buf <= n;

                     end if;

        when cal_k => if b_buf(1023) = '0' then

                        k <= k - 1;

                        b_buf <= b_buf(1022 downto 0) & '0';

                      end if;

        when mult1 => if mult_ready = '1' then

                        mult_start <= '1';

                        a_i <= a_buf;

                        b_i <= e_buf;

                      end if;

                      if m_valid_i = '1' then

                        e_buf <= m_i;

                        b_buf <= b_buf(1022 downto 0) & '0';

                        k <= k - 1;

                      end if;

        when mult2 => if mult_ready = '1' then

                        mult_start <= '1';

                        a_i <= e_buf;

                        b_i <= e_buf;

                      end if;

                      if m_valid_i = '1' then

                        e_buf <= m_i;