Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 11

                     d <= (others => '0');

                     r <= (others => '0');

                     a_part <= (others => '0');

                     a_buf <= (others => '0');

                     b_buf <= (others => '0');

                     d_buf <= (others => '0');

                     j <= 1;

                     if reset_l_1 = '1' and start = '1' then

                       ready <= '0';

                       a_buf <= a;

                       b_buf <= b;

                     end if;

        when cal_k => if a_buf(1023) = '0' then

                        k <= k - 1;

                        a_buf <= a_buf(1022 downto 0) & '0';

                        d_buf <= d_buf(1022 downto 0) & '0';

                      end if;

        when shift => if k >= j then

                        j <= j - 1;

                        k <= k - 1;

                        a_part <= a_part(10 downto 0) & a_buf(1023);

                        a_buf <= a_buf(1022 downto 0) & '0';

                        d_buf <= d_buf(1022 downto 0) & '0';

                      end if;

        when sub => j <= 1;

                      if a_part >= b_buf then

                        d_buf(0) <= '1';

                        a_part <= a_part - b_buf;

                      end if;

        when output => d_valid <= '1';

                       d <= d_buf;

                       r <= a_part;

        when others => null;

      end case;

    end if;

  end if;

end process;

end architecture;

Текст файла « gcd.vhd» :

-- find b where gcd(a,b) = 1, a > b

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity gcd is

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        out_valid : out std_logic;

        d: OUT std_logic_VECTOR(1023 downto 0);

        e: OUT std_logic_VECTOR(1023 downto 0));

end gcd;

architecture my_gcd of gcd is

component div_1024

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(11 downto 0);

        d_valid : out std_logic;

        d: OUT std_logic_VECTOR(1023 downto 0);

        r: OUT std_logic_VECTOR(11 downto 0)); -- remainder

end component;

component mult_1024

        port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        m_valid : out std_logic;

        m: OUT std_logic_VECTOR(1023 downto 0));

end component;

component add_sub_1024

        port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        C_IN: IN std_logic;

        C_OUT: OUT std_logic;

        ADD: IN std_logic;

        s_valid : out std_logic;

        S: OUT std_logic_VECTOR(1023 downto 0));

end component;

component prime_rom

        port (

        addr: IN std_logic_VECTOR(8 downto 0);

        clk: IN std_logic;

        dout: OUT std_logic_VECTOR(11 downto 0);

        en: IN std_logic);

end component;

signal a_buf, q : std_logic_vector(1023 downto 0);

signal a2, b2 : std_logic_vector(1023 downto 0);

signal a3, b3, q_tmp: std_logic_vector(11 downto 0);

signal div_start_i, div_ready_i, d_valid_i : std_logic;

signal d_i : std_logic_vector(1023 downto 0);

signal r_i : std_logic_vector(11 downto 0);

signal addr : std_logic_vector(8 downto 0);

signal b_buf : std_logic_vector(11 downto 0);

signal rd_en : std_logic;

signal m_i, m_buf, s_i : std_logic_vector(1023 downto 0);

signal mul_start_i, mul_ready_i, m_valid_i : std_logic;

signal add_start_i, add_ready_i, s_valid_i : std_logic;