signal data : std_logic_vector(11 downto 0);
signal reset_l_1 : std_logic;
type gcd_state is (idle, fetch_b, get_b, div_1, mul, add, test, div_2, output);
signal state, nxstate : gcd_state;
begin
my_div: div_1024
port map(
clk => clk,
reset_l => reset_l_1,
start => div_start_i,
ready => div_ready_i,
A => a_buf,
B => b_buf,
d_valid => d_valid_i,
d => d_i,
r => r_i); -- remainder
my_mult : mult_1024
port map (
clk => clk,
reset_l => reset_l_1,
start => mul_start_i,
ready => mul_ready_i,
A => q,
B => b2,
m_valid => m_valid_i,
m => m_i);
my_add_sub : add_sub_1024
port map (
clk => clk,
reset_l => reset_l_1,
start => add_start_i,
ready => add_ready_i,
A => a2,
B => m_buf,
C_IN => '0',
C_OUT => open,
ADD => '1',
s_valid => s_valid_i,
S => s_i);
my_prime_rom : prime_rom
port map(
addr => addr,
clk => clk,
dout => data,
en => rd_en);
process(clk)
begin
if clk'event and clk = '1' then
reset_l_1 <= reset_l;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset_l_1 = '0' then
state <= idle;
else
state <= nxstate;
end if;
end if;
end process;
gcd_fsm: process(state, reset_l_1, start, d_valid_i, m_valid_i, s_valid_i, a3,b3)
begin
nxstate <= state;
case state is
when idle => if reset_l_1 = '1' and start = '1' then
nxstate <= fetch_b;
end if;
when fetch_b => nxstate <= get_b;
when get_b => nxstate <= div_1;
when div_1 => if d_valid_i = '1' then
nxstate <= mul;
end if;
when mul => if m_valid_i = '1' then
nxstate <= add;
end if;
when add => if s_valid_i = '1' then
nxstate <= test;
end if;
when test => if b3 = x"000" then
nxstate <= fetch_b;
elsif b3 = x"001" then
nxstate <= output;
else
nxstate <= div_2;
end if;
when div_2 => if a3 < b3 then
nxstate <= mul;
end if;
when output => nxstate <= idle;
when others => nxstate <= idle;
end case;
end process gcd_fsm;
process(clk)
begin
if clk'event and clk = '1' then
if reset_l_1 = '0' then
d <= (others => '0');
e <= (others => '0');
q <= (others => '0');
q_tmp <= (others => '0');
out_valid <= '0';
ready <= '0';
a_buf <= (others => '0');
m_buf <= (others => '0');
a2 <= (others => '0');
a3 <= (others => '0');
b2 <= (others => '0');
b3 <= (others => '0');
div_start_i <= '0';
mul_start_i <= '0';
add_start_i <= '0';
b_buf <= (others => '0');
addr <= (others => '0');
rd_en <= '0';
else
ready <= '0';
out_valid <= '0';
rd_en <= '0';
div_start_i <= '0';
mul_start_i <= '0';
add_start_i <= '0';
case state is
when idle => ready <= '1';
d <= (others => '0');
e <= (others => '0');
a_buf <= (others => '0');
a2 <= (others => '0');
b2 <= (others => '0');
addr <= (others => '0');
if reset_l_1 = '1' and start = '1' then
ready <= '0';
a_buf <= a;
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