Структурные и поведенческие модели цифрового узла в пакетах DesignLab 8, OrCAD 9.1, Active HDL 6.1, страница 14

elsif (\OE_-1\ = '0' and \O_-1\'DELAYED = '1') then \O_-1\ <= 'Z' after 31ns;

elsif (\OE_-1\ = '0') then \O_-1\ <= 'Z' after 22ns;

else

    if (\I_-1\ = '0' and \O_-1\'DELAYED = '1') THEN \O_-1\ <= '0' after 15ns;

    elsif (\I_-1\ = '1' and \O_-1\'DELAYED = '0') THEN \O_-1\ <= '1' after 10ns;

    else \O_-1\ <= \I_-1\ after 15ns;

    end if;    

end if;

if (\OE_-2\ = '0' and \O_-2\'DELAYED = '0') then \O_-2\ <= 'Z' after 22ns;

elsif (\OE_-2\ = '0' and \O_-2\'DELAYED = '1') then \O_-2\ <= 'Z' after 31ns;

elsif (\OE_-2\ = '0') then \O_-2\ <= 'Z' after 22ns;

else

    if (\I_-2\ = '0' and \O_-2\'DELAYED = '1') THEN \O_-2\ <= '0' after 15ns;

    elsif (\I_-2\ = '1' and \O_-2\'DELAYED = '0') THEN \O_-2\ <= '1' after 10ns;

    else \O_-2\ <= \I_-2\ after 15ns;

    end if;  

end if;

if (\OE_-3\ = '0' and \O_-3\'DELAYED = '0') then \O_-3\ <= 'Z' after 22ns;

elsif (\OE_-3\ = '0' and \O_-3\'DELAYED = '1') then \O_-3\ <= 'Z' after 31ns;

elsif (\OE_-3\ = '0') then \O_-3\ <= 'Z' after 22ns;

else

    if (\I_-3\ = '0' and \O_-3\'DELAYED = '1') THEN \O_-3\ <= '0' after 15ns;

    elsif (\I_-3\ = '1' and \O_-3\'DELAYED = '0') THEN \O_-3\ <= '1' after 10ns;

    else \O_-3\ <= \I_-3\ after 15ns;

    end if;     

end if;

if (\OE_-4\ = '0' and \O_-4\'DELAYED = '0') then \O_-4\ <= 'Z' after 22ns;

elsif (\OE_-4\ = '0' and \O_-4\'DELAYED = '1') then \O_-4\ <= 'Z' after 31ns;

elsif (\OE_-4\ = '0') then \O_-4\ <= 'Z' after 22ns;

else

    if (\I_-4\ = '0' and \O_-4\'DELAYED = '1') THEN \O_-4\ <= '0' after 15ns;

    elsif (\I_-4\ = '1' and \O_-4\'DELAYED = '0') THEN \O_-4\ <= '1' after 10ns;

    else \O_-4\ <= \I_-4\ after 15ns;

    end if;   

end if;

   END PROCESS;

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \KR1533KP15M\ IS PORT(

D0 : IN  std_logic;

D1 : IN  std_logic;

D2 : IN  std_logic;

D3 : IN  std_logic;

D4 : IN  std_logic;

D5 : IN  std_logic;

D6 : IN  std_logic;

D7 : IN  std_logic;

S0 : IN  std_logic;

S1 : IN  std_logic;

S2 : IN  std_logic;

NEZ : IN  std_logic;

Q : OUT  std_logic;

NQ : OUT  std_logic);

END \KR1533KP15M\;

ARCHITECTURE model OF \KR1533KP15M\ IS

signal S : std_logic_vector(2 downto 0);   

BEGIN       

S <= S2&S1&S0;        

PROCESS(NEZ,D0,D1,D2,D3,D4,D5,D6,D7,S)

    variable PREQ: std_logic;           

    BEGIN 

            case S is

                when "000" => PREQ:= D0;

                when "001" => PREQ:= D1;

                when "010" => PREQ:= D2;

                when "011" => PREQ:= D3;

                when "100" => PREQ:= D4;

                when "101" => PREQ:= D5;

                when "110" => PREQ:= D6;

                when "111" => PREQ:= D7;

            end case;

    IF (Q'DELAYED = '1' OR Q'DELAYED = '0')    THEN           

        IF (NEZ='1' AND Q'DELAYED ='0') then    

            Q<= 'Z' after 22NS;  

            NQ<= 'Z' after 34NS;  

        ELSIF (NEZ='1' AND Q'DELAYED ='1') then    

            Q<= 'Z' after 31NS;  

            NQ<= 'Z' after 22NS;  

        ELSIF (S'EVENT AND Q'DELAYED='0') THEN

            Q <=PREQ AFTER 18NS;    

            NQ <=NOT(PREQ) AFTER 23NS;   

        ELSIF (S'EVENT AND Q'DELAYED='1') THEN

            Q <=PREQ AFTER 23NS;    

            NQ <=NOT(PREQ) AFTER 23NS;   

        ELSIF ((D0'EVENT OR D1'EVENT OR D2'EVENT OR D3'EVENT OR D4'EVENT OR D5'EVENT OR D6'EVENT OR D7'EVENT)  AND Q'DELAYED='0') THEN

            Q <=PREQ AFTER 10NS;

            NQ <=NOT(PREQ) AFTER 15NS;

        ELSIF ((D0'EVENT OR D1'EVENT OR D2'EVENT OR D3'EVENT OR D4'EVENT OR D5'EVENT OR D6'EVENT OR D7'EVENT)  AND Q'DELAYED='1') THEN

            Q <=PREQ AFTER 15NS;

            NQ <=NOT(PREQ) AFTER 15NS;

        END IF;       

    ELSE     

        IF (NEZ='1') then    

            Q<= 'Z';      

            NQ<= 'Z';

        ELSIF (NEZ='0') then    

            Q<=PREQ AFTER 15NS;  

            NQ<=NOT(PREQ) AFTER 15NS;  

        end if;  

    END IF;

END PROCESS;                                        

END model;