Структурные и поведенческие модели цифрового узла в пакетах DesignLab 8, OrCAD 9.1, Active HDL 6.1, страница 13

    \OUT_-3\ <= '1' AFTER TPLH WHEN NOT( \IN_-3\ )='1' ELSE '0' AFTER TPHL;

    \OUT_-4\ <= '1' AFTER TPLH WHEN NOT( \IN_-4\ )='1' ELSE '0' AFTER TPHL;

    \OUT_-5\ <= '1' AFTER TPLH WHEN NOT( \IN_-5\ )='1' ELSE '0' AFTER TPHL;

    \OUT_-6\ <= '1' AFTER TPLH WHEN NOT( \IN_-6\ )='1' ELSE '0' AFTER TPHL;

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LA2\ IS

GENERIC(TPLH: TIME := 0NS;

        TPHL: TIME := 0NS);

PORT(

IN1 : IN  std_logic;

IN2 : IN  std_logic;

IN3 : IN  std_logic;

IN4 : IN  std_logic;

IN5 : IN  std_logic;

IN6 : IN  std_logic;

IN7 : IN  std_logic;

IN8 : IN  std_logic;

\OUT\ : OUT  std_logic;

VCC : IN  std_logic;

GND : IN  std_logic);

END \K555LA2\;

ARCHITECTURE model OF \K555LA2\ IS

    BEGIN

    \OUT\ <= '1' AFTER TPLH WHEN NOT( IN1 AND IN2 AND IN3 AND IN4 AND IN5 AND IN6 AND IN7 AND IN8 )='1'

                             ELSE '0' AFTER TPHL;

END model; 

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \DELAY_ELEM\ IS

GENERIC(TPLH: TIME := 8NS;

        TPHL: TIME := 8NS);

PORT(

\IN\ : IN  std_logic;

\OUT\ : OUT  std_logic);

END \DELAY_ELEM\;

ARCHITECTURE model OF \DELAY_ELEM\ IS

    BEGIN

    \OUT\ <= '1' AFTER TPLH WHEN (\IN\)='1' ELSE '0' AFTER TPHL;

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \DELAY_ELEM2\ IS

GENERIC(TPLH: TIME := 0NS;

        TPHL: TIME := 0NS);

PORT(

\IN\ : IN  std_logic;

\OUT\ : OUT  std_logic);

END \DELAY_ELEM2\;

ARCHITECTURE model OF \DELAY_ELEM2\ IS

    BEGIN

    \OUT\ <= '1' AFTER TPLH WHEN (\IN\)='1' ELSE '0' AFTER TPHL;

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \HI\ IS

PORT(

\OUT\ : OUT  std_logic);

END \HI\;

ARCHITECTURE model OF \HI\ IS

    BEGIN

    \OUT\ <= '1';

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K155LP14\ IS PORT(

\I_-1\ : IN  std_logic;

\I_-2\ : IN  std_logic;

\I_-3\ : IN  std_logic;

\I_-4\ : IN  std_logic;

\O_-1\ : OUT  std_logic;

\O_-2\ : OUT  std_logic;

\O_-3\ : OUT  std_logic;

\O_-4\ : OUT  std_logic;

VCC : IN  std_logic;

\OE_-1\ : IN  std_logic;

\OE_-2\ : IN  std_logic;

\OE_-3\ : IN  std_logic;

\OE_-4\ : IN  std_logic;

GND : IN  std_logic);

END \K155LP14\;

ARCHITECTURE model OF \K155LP14\ IS

    BEGIN  

    PROCESS(\I_-1\,\I_-2\,\I_-3\,\I_-4\,\OE_-1\,\OE_-2\,\OE_-3\,\OE_-4\)

     BEGIN

if (\OE_-1\ = '0' and \O_-1\'DELAYED = '0') then \O_-1\ <= 'Z' after 22ns;

elsif (\OE_-1\ = '0' and \O_-1\'DELAYED = '1') then \O_-1\ <= 'Z' after 34ns;

elsif (\OE_-1\ = '0') then \O_-1\ <= 'Z' after 22ns;

else \O_-1\ <= \I_-1\ after 15ns;

end if;

if (\OE_-2\ = '0' and \O_-2\'DELAYED = '0') then \O_-2\ <= 'Z' after 22ns;

elsif (\OE_-2\ = '0' and \O_-2\'DELAYED = '1') then \O_-2\ <= 'Z' after 34ns;

elsif (\OE_-2\ = '0') then \O_-2\ <= 'Z' after 22ns;

else \O_-2\ <= \I_-2\ after 15ns;

end if;

if (\OE_-3\ = '0' and \O_-3\'DELAYED = '0') then \O_-3\ <= 'Z' after 22ns;

elsif (\OE_-3\ = '0' and \O_-3\'DELAYED = '1') then \O_-3\ <= 'Z' after 34ns;

elsif (\OE_-3\ = '0') then \O_-3\ <= 'Z' after 22ns;

else \O_-3\ <= \I_-3\ after 15ns;

end if;

if (\OE_-4\ = '0' and \O_-4\'DELAYED = '0') then \O_-4\ <= 'Z' after 22ns;

elsif (\OE_-4\ = '0' and \O_-4\'DELAYED = '1') then \O_-4\ <= 'Z' after 34ns;

elsif (\OE_-4\ = '0') then \O_-4\ <= 'Z' after 22ns;

else \O_-4\ <= \I_-4\ after 15ns;

end if;

   END PROCESS;

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K155LP14A\ IS PORT(

\I_-1\ : IN  std_logic;

\I_-2\ : IN  std_logic;

\I_-3\ : IN  std_logic;

\I_-4\ : IN  std_logic;

\O_-1\ : OUT  std_logic;

\O_-2\ : OUT  std_logic;

\O_-3\ : OUT  std_logic;

\O_-4\ : OUT  std_logic;

VCC : IN  std_logic;

\OE_-1\ : IN  std_logic;

\OE_-2\ : IN  std_logic;

\OE_-3\ : IN  std_logic;

\OE_-4\ : IN  std_logic;

GND : IN  std_logic);

END \K155LP14A\;

ARCHITECTURE model OF \K155LP14A\ IS

    BEGIN  

    PROCESS(\I_-1\,\I_-2\,\I_-3\,\I_-4\,\OE_-1\,\OE_-2\,\OE_-3\,\OE_-4\)

     BEGIN

if (\OE_-1\ = '0' and \O_-1\'DELAYED = '0') then \O_-1\ <= 'Z' after 22ns;