Bit Position |
Bit Name |
Description |
2 |
RSTD |
DSP Soft Reset When written to a 1, causes a soft reset to this DSP. Retains a 1 until cleared by writing to a 0. If the DSP core is powered down, it must be powered up first (DSP:PU bit written to 1) before resetting. |
3 |
FIEN |
DSP Interrupt Enable: AC’97 Frame When 1, enables an AC’97 Frame interrupt (IMASK bit 15) to this DSP from the AC’97 Interface. If 0, no interrupt is signalled (Read/Write). The actual interrupt occurs once per AC’97 Frame, at the second bit of Slot 12. |
4 |
PMWE |
Power Management Wakeup Enable. When 1, enables waking the respective DSP on a Power Management State Change event (Read/Write). |
5 |
AWE |
DSP Wakeup Enable: GPIO Interrupt, AC’97 Interrupt. When 1, enables this DSP to wake from powerdown upon an event from the indicated source. (Read/Write). |
6 |
GWE |
DSP Wakeup Enable: GPIO Interrupt, AC’97 Interrupt. When 1, enables this DSP to wake from powerdown upon an event from the indicated source. (Read/Write). |
7 |
RWE |
DSP Wakeup Enable: GPIO Interrupt, AC’97 Interrupt. When 1, enables this DSP to wake from powerdown upon an event from the indicated source. (Read/Write). |
8 |
PMIEN |
Power Management Interrupt Enable. When 1, enables interrupting the respective DSP on a Power Management State Change event. (The interrupt level is the same as used for GPIO and AC’97 interrupt) (Read / Write). |
Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions (Continued)
Bit Position |
Bit Name |
Description |
9 |
AIEN |
DSP Interrupt Enable: AC’97 Interrupt. When 1, enables an IO interrupt to this DSP from the AC’97 port. If 0, no interrupt will be signalled and the corresponding Interrupt Pending bit will not be set upon an event. (Read/Write). |
10 |
GIEN |
DSP Interrupt Enable: GPIO Interrupt. When 1, enables an IO interrupt to this DSP from the GPIO. If 0, no interrupt will be signalled and the corresponding Interrupt Pending bit will not be set upon an event. (Read/Write). |
11 |
Reserved |
|
12 |
PMINT |
Power Management Interrupt Pending. When 1, indicates an interrupt is pending for the respective DSP from a Power Management State Change event. A write of 1 clears this interrupt flag. A write of 0 has no effect. |
13 |
AINT |
When 1, an IO interrupt (IMASK bit 6) to this DSP is pending from the AC’97 port. A write of 1 clears this interrupt flag. A write of 0 has no effect. The AC’97 port should be cleared prior to clearing this interrupt flag, or it may be re-triggered. Similarly, this interrupt flag must be cleared prior to executing an RTI from the DSP interrupt handler routine, or the DSP may immediately take another interrupt. |
14 |
GINT |
When 1, an IO interrupt (IMASK bit 6) to this DSP is pending from the GPIO. A write of 1 clears this interrupt flag. A write of 0 has no effect. The GPIO should be cleared first (e.g., clearing a GPIO Status Bit) prior to clearing this interrupt flag, or it may be re-triggered. Similarly, this interrupt flag must be cleared prior to executing an RTI from the DSP interrupt handler routine, or the DSP may immediately take another interrupt. |
15 |
Reserved |
DSP PLL C ontrol (PLLC TL) Re g iste r
The DSP PLL control register controls the frequencies of the PLL (Phase Locked Loop) clock generator. Do not write to this register unless the PLL is powered down.
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