|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table B-23. PCI_IRQSTAT Register Bit Descriptions
|
Bit position |
Bit name |
Description |
|
0 |
Reserved |
|
|
1 |
RX0 DMA |
Rx0 DMA Channel Interrupt. Receive Channel 0 Bus Master Transactions Sensitivity: Edge |
|
2 |
RX1 DMA |
Rx1 DMA Channel Interrupt. Receive Channel 1 Bus Master Transactions Sensitivity: Edge |
|
3 |
TX0 DMA |
Tx0 DMA Channel Interrupt. Transmit Channel 0 Bus Master Transactions Sensitivity: Edge |
|
4 |
Tx1 DMA |
Tx1 DMA Channel Interrupt. Transmit Channel 1 Bus Master Transactions Sensitivity: Edge |
Table B-23. PCI_IRQSTAT Register Bit Descriptions (Continued)
|
Bit position |
Bit name |
Description |
|
5 |
MBox 0 IN |
Incoming Mailbox 0 PCI Interrupt. PCI to DSP Mailbox 0 Transfer Sensitivity: Edge |
|
6 |
MBox 1 IN |
Incoming Mailbox 1 PCI Interrupt. PCI to DSP Mailbox 1 Transfer Sensitivity: Edge |
|
7 |
MBox 0 OUT |
Outgoing Mailbox 0 PCI Interrupt. DSP to PCI Mailbox 0 Transfer Sensitivity: Edge |
|
8 |
MBox 1 OUT |
Outgoing Mailbox 1 PCI Interrupt. DSP to PCI Mailbox 1 Transfer Sensitivity: Edge |
|
9 |
Reserved |
|
|
10 |
Reserved |
Reserved |
|
11 |
GPIO |
General Purpose I/O Pin Initiated. Sensitivity: Level |
|
12 |
AC’97 |
AC’97 Interface Initiated. Sensitivity: Edge |
|
13 |
Master Abort |
PCI Interface Master Abort Detected. Sensitivity: Edge |
|
14 |
Target Abort |
PCI Interface Target Abort Detected. Sensitivity: Edge |
|
15 |
Reserved |
|
PC I C ontrol (PC I_C FG C TL) Re g iste r
! All bits in this register reset to 0.
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table B-24. PCI_CFGCTL Register Bit Descriptions
|
Bit position |
Bit name |
Description |
|
1-0 |
PCIF[1:0] |
PCI Functions Configured. 00 = One PCI Function enabled 01= Two functions 10= Three functions |
|
2 |
Conf Rdy |
Configuration Ready. When 0, disables PCI accesses to the ADSP-2192 (terminated with Retry). Must be set to 1 by DSP ROM code after initializing configuration space. Once 1, cannot be written to 0. |
|
4:3 |
Reserved |
|
|
5 |
P2DM0 IEN |
PCI to DSP Mailbox 0 Transfer Interrupt Enabled. |
|
6 |
P2DM1 IEN |
PCI to DSP Mailbox 1 Transfer Interrupt Enabled. |
|
7 |
D2PM0 IEN |
DSP to PCI Mailbox 0 Transfer Interrupt Enabled. |
|
8 |
D2PM1 IEN |
DSP to PCI Mailbox 1 Transfer Interrupt Enabled. |
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