PC I C onfig ura tion Re g iste r Sp a c e , Func tion 2
PCI Configuration Spaces should be accessed only by the DSP, and only during the boot process. After the PCI interface has been configured, bit 2 of the PCI_CFGCTL register (ConfRdy) should be set by the DSP. This allows the PCI interface access to these registers while at the same time denying the DSP access.
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Access to these registers is controlled by the PCI RDY bit in the PCI Interrupt Control Register (Page 0x08, Address 0xA2). See
“General Purpose I/O (GPIO) Control Registers” on page B-24.
Table B-27. Function 2 Registers
Register Name |
Description |
PCI Address |
USB Address |
DSP I/O Page |
DSP I/O Address |
PCI_CFG2_VID |
Config2 Vendor ID |
0x01-0x00 |
n/a |
0x0B |
0x00 |
PCI_CFG2_DID |
Config2 Device ID |
0x03-0x02 |
n/a |
0x0B |
0x02 |
PCI_CFG2_CCODEL |
Config2 Class Code[7:0],Rev ID |
0x08 |
n/a |
0x0B |
0x08 |
Table B-27. Function 2 Registers (Continued)
Register Name |
Description |
PCI Address |
USB Address |
DSP I/O Page |
DSP I/O Address |
PCI_CFG2_CCODEH |
Config2 Class Code[23:8] |
0x0B-0x0A |
n/a |
0x0B |
0x0A |
PCI_CFG2_SVID |
Config2 Subsystem Vendor ID |
0x2D-0x2C |
n/a |
0x0B |
0x2C |
PCI_CFG2_SDID |
Config2 Subsystem Device ID |
0x2F-0x2E |
n/a |
0x0B |
0x2E |
PCI_CFG2_PWRMT |
Config2 Power Mgt Capabilities. Bit 15 set if Vaux is sensed valid. |
0x45-0x44 |
n/a |
0x0B |
0x44 |
PC I C onfig ura tion Sp a c e
Table B-28 on page B-60, Table B-29 on page B-63, and Table B-30 on page B-65 show the PCI Configuration Space definitions for functions 0, 1, and 2.
Table B-28. PCI CONFIG SPACE for Function 0
Address |
Name |
Reset |
Comments |
0x01-0x00 |
Vendor ID |
0x11D4 |
Writable from the DSP during initialization |
0x03-0x02 |
Device ID |
0x2192 |
Writable from the DSP during initialization |
Table B-28. PCI CONFIG SPACE for Function 0 (Continued)
Address |
Name |
Reset |
Comments |
0x05-0x04 |
Command Register |
0x0 |
Bus Master, Memory Space Capable, I/O Space Capable |
0x07-0x06 |
Status Register |
0x0 |
Bits enabled: Capabilities List, Fast B2B, Medium Decode |
0x08 |
Revision ID |
0x0 |
Writable from the DSP during initialization |
0x0B-0x09 |
Class Code |
0x078000 |
Writable from the DSP during initialization |
0x0C |
Cache Line Size |
0x0 |
Read-only |
0x0D |
Latency Timer |
0x0 |
|
0x0E |
Header Type |
0x80 |
Multifunction bit set |
0x0F |
BIST |
0x0 |
Unimplemented |
0x13-0x10 |
Base Address 1 |
0x08 |
Register Access for all ADSP-2192 Registers, Prefetchable Memory |
0x17-0x14 |
Base Address 2 |
0x08 |
24-bit DSP Memory Access |
0x1B-0x18 |
Base Address 3 |
0x08 |
16-bit DSP Memory Access |
0x1F-0x1C |
Base Address 4 |
0x01 |
I/O access for control registers and DSP memory |
0x23-0x20 |
Base Address 5 |
0x0 |
Unimplemented |
0x27-0x24 |
Base Address 6 |
0x0 |
Unimplemented |
0x2B-0x28 |
Cardbus CIS Pointer |
0x1FF03 |
CIS RAM Pointer - Function 0 (Read Only). |
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