#define PCI_DeviceID0 0x02 // Configuration 0 Device ID
#defineP CI_ClassCODE0L 0x08//C onfiguration 0ClassC ode[7:0],Rev ID #define PCI_ClassCODE0H 0x0A // Configuration 0 Class Code[23:8] #define PCI_SVendorID0 0x2C // Configuration 0 Subsystem Vendor ID
#define PCI_SDeviceID0 0x2E // Configuration 0 Subsystem Device ID #define PCI_PWRMT0 0x44 // Configuration 0
// Power Mgt Capabilities Bit 15 set if Vaux is sensed valid.
// PCI FUNCTION 1 Configuration Space Registers (DSP IOPAGE=0x0A)
// Note: Access to these registers is controlled by the PCI RDY bit in the // Chip Mode/Status Register (Page 0x00, Address 0x00).
#define PCI_VendorID1 0x00 // Configuration 1 Vendor ID
#define PCI_DeviceID1 0x02 // Configuration 1 Device ID #define PCI_ClassCODE1L 0x08 // Configuration 1 Class
Code[7:0], Rev ID
#define PCI_ClassCODE1H 0x0A // Configuration 1 Class
Code[23:8]
#define PCI_SvendorID1 0x2C // Configuration 1 Subsystem
Vendor ID
#define PCI_SdeviceID1 0x2E // Configuration 1 Subsystem
Device ID
#define PCI_PWRMT1 0x44 // Configuration 1
// Power Mgt Capabilities Bit 15 set if Vaux is sensed valid.
// PCI FUNCTION 2 Configuration Space Registers (DSP IOPAGE=0x0B)
// Note: Access to these registers is controlled by the PCI RDY bit in the
// PCI Interrupt Control Register ( Page 0x08, Address 0xA2 ).
#define PCI_VendorID2 0x00 // Configuration 2 Vendor ID
#define PCI_DeviceID2 0x02 // Configuration 2 Device ID
#define PCI_ClassCODE2L 0x08 // Configuration 2 Class
Code[7:0],Rev ID
#define PCI_ClassCODE2H 0x0A // Configuration 2 Class
Code[23:8]
#define PCI_SvendorID2 0x2C // Configuration 2 Subsystem
Vendor ID
#define PCI_SdeviceID2 0x2E // Configuration 2 Subsystem
Device ID
#define PCI_PWRMT2 0x44 // Configuration 2 Power Mgt // Capabilities Bit 15 set if Vaux is sensed valid.
// USB Endpoint DMA Control Registers (DSP IOPAGE=0x0C)
#define USB_EP4_ADDR 0x00 // Memory Buffer Base Addr. EP4
#define USB_EP4_SIZE 0x04 // Memory Buffer Size EP4
#define USB_EP4_RD 0x06 // Memory Buffer RD Offset EP4
#define USB_EP4_WR 0x08 // Memory Buffer WR Offset EP4
#define USB_EP5_ADDR 0x10 // Memory Buffer Base Addr. EP5
#define USB_EP5_SIZE 0x14 // Memory Buffer Size EP5
#define USB_EP5_RD 0x16 // Memory Buffer RD Offset EP5
#define USB_EP5_WR 0x18 // Memory Buffer WR Offset EP5
#define USB_EP6_ADDR 0x20 // Memory Buffer Base Addr. EP6 #define USB_EP6_SIZE 0x24 // Memory Buffer Size EP6
#define USB_EP6_RD 0x26 // Memory Buffer RD Offset EP6
#define USB_EP6_WR 0x28 // Memory Buffer WR Offset EP6
#define USB_EP7_ADDR 0x30 // Memory Buffer Base Addr. EP7
#define USB_EP7_SIZE 0x34 // Memory Buffer Size EP7
#define USB_EP7_RD 0x36 // Memory Buffer RD Offset EP7
#define USB_EP7_WR 0x38 // Memory Buffer WR Offset EP7
#define USB_EP8_ADDR 0x40 // Memory Buffer Base Addr. EP8
#define USB_EP8_SIZE 0x44 // Memory Buffer Size EP8
#define USB_EP8_RD 0x46 // Memory Buffer RD Offset EP8
#define USB_EP8_WR 0x48 // Memory Buffer WR Offset EP8
#define USB_EP9_ADDR 0x50 // Memory Buffer Base Addr. EP9
#define USB_EP9_SIZE 0x54 // Memory Buffer Size EP9
#define USB_EP9_RD 0x56 // Memory Buffer RD Offset EP9
#define USB_EP9_WR 0x58 // Memory Buffer WR Offset EP9
#define USB_EP10_ADDR 0x60 // Memory Buffer Base Addr. EP10
#define USB_EP10_SIZE 0x64 // Memory Buffer Size EP10
#define USB_EP10_RD 0x66 // Memory Buffer RD Offset EP10
#define USB_EP10_WR 0x68 // Memory Buffer WR Offset EP10
#define USB_EP11_ADDR 0x70 // Memory Buffer Base Addr. EP11
#define USB_EP11_SIZE 0x74 // Memory Buffer Size EP11
#define USB_EP11_RD 0x76 // Memory Buffer RD Offset EP11
#define USB_EP11_WR 0x78 // Memory Buffer WR Offset EP11
#endif
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