Table B-32. Power Management Register Interactions Between Functions (Continued)
Name |
Comments |
||
Data Scale |
14-13 |
Read-only, no interaction |
|
PME Status |
15 |
Separate for each function, may be set in all functions by a wakeup |
O ve rvie w
The USB registers control the USB interface, specifically the operation and configuration of the USB Interface. Most of these registers are accessible only via the USB Bus, although a subset is accessible to the DSP.
The ADSP-2192 USB allows you to configure and attach a single device with multiple interfaces and various endpoint configurations. The advantages to this design are:
• Programmable descriptors and class specific command interpreter. An MCU is supported on board, which allows you to soft download different configurations and support any number of standard or class specific commands.
• Eight user defined endpoints are provided. Endpoints can be configured as either BULK, ISO, or INT and can be grouped and assigned to any interface.
For each endpoint, four registers are defined in order to provide a memory buffer in the DSP. These registers are defined for each endpoint shared by all interfaces that are defined for a total of 4x8 = 32 registers. These registers are read/write by the DSP only.
Table B-33. USB DSP Register Definitions
Page |
Address |
Name |
0x0C |
0x00-0x03 |
DSP Memory Buffer Base Addr EP4 |
0x0C |
0x04-0x05 |
DSP Memory Buffer Size EP4 |
0x0C |
0x06-0x07 |
DSP Memory Buffer RD Offset EP4 |
0x0C |
0x08-0x09 |
DSP Memory Buffer WR Offset EP4 |
0x0C |
0x10-0x13 |
DSP Memory Buffer Base Addr EP5 |
0x0C |
0x14-0x15 |
DSP Memory Buffer Size EP5 |
0x0C |
0x16-0x17 |
DSP Memory Buffer RD Offset EP5 |
0x0C |
0x18-0x19 |
DSP Memory Buffer WR Offset EP5 |
0x0C |
0x20-0x23 |
DSP Memory Buffer Base Addr EP6 |
0x0C |
0x24-0x25 |
DSP Memory Buffer Size EP6 |
0x0C |
0x26-0x27 |
DSP Memory Buffer RD Offset EP6 |
0x0C |
0x28-0x29 |
DSP Memory Buffer WR Offset EP6 |
0x0C |
0x30-0x33 |
DSP Memory Buffer Base Addr EP7 |
0x0C |
0x34-0x35 |
DSP Memory Buffer Size EP7 |
0x0C |
0x36-0x37 |
DSP Memory Buffer RD Offset EP7 |
0x0C |
0x38-0x39 |
DSP Memory Buffer WR Offset EP7 |
0x0C |
0x40-0x43 |
DSP Memory Buffer Base Addr EP8 |
Table B-33. USB DSP Register Definitions (Continued)
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