Address |
Register |
Function |
4A |
TX0CNT |
DMA Count, FIFO0 Transmit |
4B |
TX0CURCNT |
DMA Current Count, FIFO0 Transmit |
4C |
RX0ADDR |
DMA Address, FIFO0 Receive |
4D |
RX0NXTADDR |
DMA Next Address, FIFO0 Receive |
4E |
RX0CNT |
DMA Count, FIFO0 Receive |
4F |
RX0CURCNT |
DMA Current Count, FIFO0 Receive |
50 |
TX1ADDR |
DMA Address, FIFO1 Transmit |
51 |
TX1NXTADDR |
DMA Next Address, FIFO1 Transmit |
52 |
TX1CNT |
DMA Count, FIFO1 Transmit |
53 |
TX1CURCNT |
DMA Current Count, FIFO1 Transmit |
54 |
RX1ADDR |
DMA Address, FIFO1 Receive |
55 |
RX1NXTADDR |
DMA Next Address, FIFO1 Receive |
56 |
RX1CNT |
DMA Count, FIFO1 Receive |
57 |
RX1CURCNT |
DMA Current Count, FIFO1 Receive |
58-5F |
Reserved |
|
60 |
DBGCTRL |
Test and Emulation Debug Control Register |
61 |
DBGSTAT |
Test and Emulation Debug Status Register |
62 |
CNT0 |
Cycle Counter 0 Register (LSB) |
63 |
CNT1 |
Cycle Counter 1 Register |
Table B-1. ADSP-2192 System Control Registers (Continued)
Address |
Register |
Function |
64 |
CNT2 |
Cycle Counter 2 Register |
65 |
CNT3 |
Cycle Counter 3 Register (MSB) |
66-FF |
Reserved |
STC TLx FIFO Tra nsm it C ontrol Re g iste r
These include the STCTL0 and STCTL1 registers in each DSP core.
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
SRC TLx FIFO Re c e ive C ontrol Re g iste r These include the SRCTL0 and SRCTL1 registers in each DSP core. |
|||||||||||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
x x x A DDR DMA A d d re ss Re g iste r
This group of registers include Rx0ADDR, Rx1ADDR, Tx0ADDR, Tx1ADDR, and MASTADDR registers for each DSP core. Each register is a 16-bit register containing a 16-bit word.
x x x NX TA DDR DMA Ne x t A d d re ss Re g iste r
This group of registers include Rx0NXTADDR, Rx1NXTADDR, Tx0NXTADDR, Tx1NXTADDR, and MASTNXTADDR for each DSP core. Each register is a 16-bit register containing a 16-bit word.
x x x C NT DMA C ount Re g iste r
This group of registers include Rx0CNT, Rx1CNT, Tx0CNT, Tx1CNT, and MASTCNT for each DSP core. Each register is a 16-bit register containing a 16-bit word.
x x x C URC NT DMA C urre nt C ount Re g iste r
This group of registers include Rx0CURCNT, Rx1CURCNT, Tx0CURCNT, Tx1CURCNT, and MASTCURCNT for each DSP core. Each register is a 16-bit register containing a 16-bit word.
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