The following tables show the Peripheral Device Control Registers accessible by both DSP cores and the PCI and USB interfaces.
The following is a summary of the various classes of I/O registers and their organization within DSP I/O pages.
! Addresses are 8-bit values. The Page is also an 8-bit value.
Table B-2. Register Group Descriptions
Page |
Addresses |
Descriptions |
Access permitted by |
Refer to |
0x00 |
0x00-0x0F |
ADSP-2192 Chip Control Registers |
DSP / PCI / USB |
page B-13 |
0x10-0x1F |
General Purpose I/O (GPIO) Control Registers |
DSP / PCI / USB |
page B-24 |
|
0x20-0x2F |
Host Mailbox Registers |
DSP / PCI / USB |
page B-30 |
|
0x30 |
EEPROM Register |
DSP / PCI / USB |
page B-28 |
|
0xA0-0xBF |
JTAG ID Registers |
DSP Only |
page B-32 |
|
0xC0-0xFF |
AC’97 Controller Registers |
DSP / PCI / USB |
page B-41 |
|
0x01 |
0x00-0x2D |
CardBus Function Event Registers |
DSP / PCI |
page B-32 |
0x02-0x03 |
Reserved |
|||
0x04 |
0x00-0x7E |
AC’97 Codec Register Space, Primary Codec 0 |
DSP / PCI / USB |
page B-45 |
Table B-2. Register Group Descriptions (Continued)
Page |
Addresses |
Descriptions |
Access permitted by |
Refer to |
0x05 |
0x00-0x7E |
AC’97 Codec Register Space, Secondary Codec 1 |
DSP / PCI / USB |
page B-45 |
0x06 |
0x00-0x7E |
AC’97 Codec Register Space, Secondary Codec 2 |
DSP / PCI / USB |
page B-46 |
0x07 |
Reserved |
|||
0x08 |
0x00-0x7F |
DMA Address, Count Registers |
DSP / PCI |
page B-46 |
0x80-0x87 |
DMA Control Registers |
DSP / PCI |
page B-46 |
|
0x88-0x8A |
PCI Interrupt, Control Registers |
DSP / PCI |
page B-47 |
|
0x09 |
0x00-0xFF |
PCI Configuration Register Space, Function 0 |
DSP1 / PCI |
page B-56 |
0x0A |
0x00-0xFF |
PCI Configuration Register Space, Function 1 |
DSP1 / PCI |
page B-58 |
0x0B |
0x00-0xFF |
PCI Configuration Register Space, Function 2 |
DSP1 / PCI |
page B-59 |
0x0C |
0x00-0x4F |
USB DSP Registers |
DSP / USB |
page B-71 |
0x0D-0xFF |
Reserved |
1 PCI configuration spaces should be accessed only by the DSP, and only during the boot process. After the PCI interface has been configured, bit 2 (ConfRdy) of the PCI_CFGCTL register should be set by the DSP. This allows the PCI interface access to these registers while at the same time denying the DSP access.
The chip control registers provide support for the following:
• General status for the chip as a whole
• Power-down operations
• Other control functions
The following table lists the PDC register space. The register addresses from PCI space, USB space, and DSP I/O space are listed.
Table B-3. ADSP-2192 Chip Control Registers
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