Детальный проект конвейерного RISC процессора (Глава 5 "Обработка прерываний"), страница 16

RTL команды      

тип I

Сигналы

IF

IR.1 = IM(DPC)

fetch, IRce

ID

A=A' = RS1, AEQZ = zero(A'),

B = RS2, PC' = (reset ? 4 : pc'), DPC= (reset ? 0 : dpc),

S = SPR[Sas],

link = PC' + 4, DDPC = DPC, IR.2 = IR.l, Sad.2 = Sad,

Ace,

Bce, PC'ce, DPCcee

Sce

PCce,

co = constant (IR.1)

j, jal, trap

Jimm

slli, srli, srai

shiftI

otherwise

(pc', dpc) = nextPC (PC' , A', co, EPCs)

rfe

rfe.l

j. jal

jump

jr, jalr

jumpR, jump

beqz

branch, bzero

bnez

branch

otherwise

Cad = Caddr(IR.1)

jalr, jal

Jlink

R-type

Rtype

otherwise

(Sas, Sad) = Saddr (IR.1)

rfe

rfe.l

otherwise

состояние

команда RTL

управляющие сигналы

EX

alu

MAR = A op B,

MDRw = shift(A,B[4:0])

ALUDdoe, Rtype, bmuxsel

aluo

MAR = A op B, overflow? MDRw = shift(A,B[4:0])

ALUDdoe, Rtype, ovf? bmuxsel

test

MAR=(A rel B ? 1 :0), MDRw = shift(A,B[4:0])

ALUDdoe, test, Rtype, bmuxsel

shift

MAR = MDRw = shift(A,B[4:0]),

SHDdoe, Rtype, bmuxsel

aluI

MAR = A op co,

ALUDdoe,

aluIo

MAR = A op co, overflow?

ALUDdoe, ovf?

testI

mar = (a rel co ? 1 :0)

ALUDdoe, test

shiftI

MAR = shift(A, co[4:0])

SHDdoe, shiftl, Rtype

savePC

MAR = link

linkDdoe,

addrL

MAR = A + co,

ALUDdoe, add,

addrS

MAR = A + co,

MDRw = cls(B, MAR[l:0]000)

ALUDdoe, add, amuxsel, shift4s

trap

MAR = co, trap = 1

coDdoe, trap

I11

MAR = A, ill = 1

ADdoe, ill

rfe

MAR = S

SDdoe

ms2i

MAR = S

SDdoe

mi2s noEX

default updates

ADdoe

M

load

MDRr =

Mword[(MAR[31:2]00)]

Dmr

store

m = bytes(MDRw)

Dmw

others

default updates

WB

sh41

GPR[Cad.4] = sh4l(MDRr,MAR[1:0]000)

shift4l, GPRw

wb

GPR[Cad.4] = C.4

GPRw

mi2sW

SPR[Sad.4] = C.4

SPRw

noWB

no update