Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 8

The ADSP-219x dual-voltage processor (ADSP-2192) has special issues related to powerup. These issues include the powerup sequence and the dual-voltage power supplies. This section discusses both of these issues. It also gives information about reset generators, which provide a reliable active reset once the power supplies and internal clock circuits have stabilized.

Powerup Sequenc e

Each of the DSPs on the ADSP-2192 has a register to control powerup and powerdown functions. These registers are PWRP0 (the DSP1 Interrupt/Powerdown Register) and PWRP1 (the DSP2 Interrupt/Powerdown Register).

To power up one of the DSPs, write a 1 to the PU (power up) control bit of that DSP’s Interrupt/Powerdown Register. Writing this value causes the DSP to exit the IDLE within its powerdown handler, effectively powering up. The same process can also be used to abort a powerdown; if the DSP is in the powerdown handler prior to the IDLE, writing a 1 causes execution to immediately continue through the IDLE without stopping the clocks.

To power down one of the DSPs, write a 1 to the PD (power down) control bit of that DSP’s Interrupt/Powerdown Register. Writing this value causes the DSP to enter its powerdown handler. The same process can be used to abort a powerup. If the DSP is in the powerdown handler after executing an IDLE, writing a 1 causes the DSP to immediately re-enter the powerdown handler after executing the RTI.

The current value of the PD and PU control bits indicate the current state of the DSP. If PD=1, this DSP is powered down; either it is in the powerdown handler and has executed an IDLE instruction, or the DSP Clock Generator (PLL) is not running and stable. If PU=1, this DSP is in the powerdown interrupt handler, whether or not it has executed the powerdown IDLE.

If both DSPs are powered down, the DSP clock generator is also powered down. The DSP clock generator restarts automatically when either DSP wakes up. DSP memory cannot be accessed via PCI when the DSP clock generator is powered down, and memory reads must not be performed while the DSPs are powering up.

The following recommendations should be observed when powering up dual-voltage DSPs. Ideally, the two supplies, V_DDEXT and V_DDINT, should be powered up together. If they cannot be powered up together, the internal (core) supply should be powered up first to reduce the risk of latchup events.

As shown in Figure 11-3 on page 11-26, a network of protection diodes, isolates the internal supplies and provides ESD protection for the IO pins.

When applying power separately to the V_DDINT or V_DDEXT pins, limit the maximum supply current and duration that would be conducted through the isolation diodes if the unpowered pins are at ground potential.

If an external master clock is used, it should not be driving the XTALI pin when the DSP is unpowered. The clock must be driven immediately after powerup; otherwise, internal gates stay in an undefined (hot) state and can draw excess current. After powerup, there should be sufficient time for the internal PLL to stabilize (2000 clock cycles) before the reset is released.

Figure 11-3. Protection Diodes and IO Pin ESD Protection

Power Reg ula tors

The ADSP-2192 is intended to operate in a variety of different systems.

These include PCI, CardBus, USB and embedded (Sub-ISA) applications. The PCI and USB specifications define power consumption limits that constrain the ADSP-2192 design; see “Host (PCI/USB) Port” on page 8-1 for more information.

2.5V Re g ula tor O p tions