Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 11

USB host then signals the SUSPEND state to the ADSP-2192. When the SUSPEND state is signaled, the USB interface sees this bus state and notifies the ADSP-2192, causing the internal USB clocks to stop, at which time the device enters its lowest power state.

Powering Down the PCI

Refer to“Power Management Functions” on page B-18 for information about powering down the PCI.

Powering Down the A C ’97 Link

The recommended way to enable and disable the link is through use of the LKEN bit. When LKEN is set to 1, the following results can occur:

•  If the link was already running (LKOK=1), there is no effect.

•  If the link was in cold reset, ACRST is deasserted (clearing ACTL:AFR if necessary).

•  If the link was in warm reset, SYNC is asserted for 1 µs and is then deasserted.

•  If BITCLK is internal, the BITCLK generator starts (ACTL:BCEN set to 1) when ACRST deasserts (cold) or when SYNC deasserts (warm). If BITCLK is external, the external primary codec must start BITCLK in a similar manner.

•  When BITCLK restarts (ASTAT:BCOK reads 1), the sync pulse generator is automatically enabled (ATL:SYEN set t o1). At this point, LKOK reads 1.

For more information about AC’97 power modes, refer to “AC’97 Codec Port” on page 9-1.

Entering Powerdown

The powerdown sequence is defined as follows:

1.  Initiate the powerdown sequence by writing a 1 to the PD bits of the PWRP1 and PWRP2 registers.

2.  The processor vectors to the non-maskable powerdown interrupt vector at address 0x002C.

The powerdown interrupt is never masked. You must be careful not to cause multiple powerdown interrupts to occur, or stack overflow may result. Multiple powerdown interrupts can occur if the PWD input is pulsed while the processor is already servicing the powerdown interrupt.)

3.  Any number of housekeeping instructions, starting at location 0x002C, can be executed prior to the processor entering the powerdown mode. Typically, this section of code is used to configure the powerdown state, disable on-chip peripherals, and clear pending interrupts.

4.  The processor enters powerdown mode when it executes an IDLE instruction (while the PD bit is set). The processor may take either one or two cycles to power down, depending on internal clock states during the execution of the IDLE instruction. All register and memory contents are maintained while in powerdown. Also, all active outputs are held in whatever state they were in before going into powerdown.

Similarly, the powerdown sequence can be aborted by writing a 1 to the PU bits of the PWRP1 and PWRP2 registers. If an RTI is executed before the IDLE instruction, then the processor returns from the powerdown interrupt and the powerdown sequence is aborted.

Exiting Powerdown

The powerdown mode can be exited with the use of the PU bit of the PWRP1 and PWRP2 registers. Writing a 1 to that bit causes the powerdown sequence to be aborted. There are also several user-selectable modes for start-up from powerdown which specify a start-up delay and also specify the program flow after start-up. This feature allows the program to resume from where it left off before powerdown, or the program context to be cleared.

End ing Powe rd own

Applying a low-to-high transition to the PU bits of the PWRP1 and PWRP2 registers takes the processor out of powerdown mode. The processor automatically selects the amount of time to wait before coming out of the powerdown mode. The PLL waits until it is stable before starting the clocks to the rest of the system; it stabilizes more quickly when the XON bit (the Xtal Force On bit in the CMSR register) is set because the crystal oscillator remains active. For more information, see “Using an External TTL/CMOS Clock” on page 11-36.

End ing Powe rd own with the PO RST Pin